No abstract

A very compact, rail-to-rail, low-power, high-speed buffer amplifier for LCD driver applications is proposed. A slew-rate enhancement technique based on a dynamic current bias scheme is adopted, and a high slew-rate is obtained without increasing the quiescent current. The buffer amplifier uses a small number of transistors and enables very small active layout area. The proposed buffer amplifier is suitable for both low-and high-voltage LCD driver applications.Introduction: As liquid-crystal displays (LCDs) approach high resolution, high quality, and physically large panel size, the design of output buffer amplifiers becomes more challenging. More specifically, the buffer amplifier needs to be faster in order to deal with larger load capacitance and resistance and thereby achieve smaller settling time. In addition, hundreds or thousands of output buffer amplifiers are integrated into one driver IC, and the buffer should occupy a small die area and consume small static power. It also should provide a rail-to-rail voltage driving capability so that higher grey levels can be accommodated.To reduce settling time, the slew-rate of the buffer amplifier should be increased, because the slewing time normally dominates the settling time in LCD applications. Several techniques have thus far been used to increase slew-rate without additional static power. Lu [1, 2] used additional comparators to sense the rising/falling edges of the input and then turn on push/pull transistors in the output stage to charge/discharge the output load. Yu and Wu [3] proposed a class B buffer in which a comparator is used in the negative feedback path to eliminate the static current in the output stage. Kim and Cho [4] adopted positive feedback loops to speed up the slew-rate of the proposed buffer when there is a voltage difference in the differential input. Choi et al. [5] developed an adaptive dynamic current biasing scheme to increase slew-rate without increasing the quiescent current. In this Letter we propose a very compact low-power high-speed rail-to-rail buffer amplifier using a slew-rate enhancement technique (SRET) based on the adaptive current biasing scheme [5].

A compact digitally-controlled single-stage variable gain amplifier (VGA) is introduced, which doubles the dB-linear range through the reconfiguration, saves power by 50% while maintaining the same linearity performance compared to those of the previous design. Implemented in 0.18 mm CMOS technology, the 5-bit digitally-controlled VGA achieves dB-linear gain range of 42 dB (221 to 21 dB) with gain error less than +0.55 dB, bandwidth of 84 MHz at maximum gain of 21 dB and maximum IIP3 of 14 dBm while consuming only 760 mA from a 1.8 V supply.

No abstract

No abstract

No abstract

A differential cyclic 10-bit DAC with multi-bit conversion per cycle architecture is presented. Passive conversion is done within 1µs and the output is driven during the rest of 1-H time. Designed in differential scheme, the switched-capacitor circuit is robust to charge injection, clock feedthrough and capacitive noise coupling. The DAC has been designed for a high voltage 0.18-µm CMOS technology.

No abstract