Combinatorial Algorithms for Fast Clock Mesh Optimization

Abstract

We present a fast and efficient combinatorial algorithm to simultaneously identify the candidate locations as well as the sizes of the buffers driving a clock mesh. Due to the high redundancy, a mesh architecture offers high tolerance towards variation in the clock skew. However, such a redundancy comes at the expense of mesh wire length and power dissipation. Based on survivable network theory, we formulate the problem to reduce the clock mesh by retaining only those edges that are critical to maintain redundancy. Such a formulation offers designer the option to trade-off between power and tolerance to process variations. Experimental results indicate that our techniques can result in power savings up to 28% with less than 4% delay penalty.

Timing-driven variation-aware nonuniform clock mesh synthesis

“…Non-uniform meshes [5], [10], [11] have been developed to save wire resources and power. Design automation and optimization of metal and power versus tolerance tradeoffs are discussed in [10], [11]. Mesh architectures differ in the locality of the mesh.…”

“…Other approaches start with a fully uniform mesh, identify and remove redundant segments whose effect on variations is minimal by applying network theory techniques, thereby trading off variations with wire length. A set-cover problem is solved to obtain mesh pre-driver minimum buffers [10], [11]. The initial uniform grid is designed to ensure that metal redundancies within the grid satisfy target skew requirements [10].…”

“…Skew as a function of mesh density has also been discussed in [10]. Optimized pre-drivers are placed by solving a set-covers problem [10], [11].…”

“…Non-tree clock distribution topologies (e.g., clock meshes) exhibit useful characteristics due to multi-path signal propagation created by routing redundancies [1][2][3][4][5][6][7][8][9][10][11]. These non-tree clock distribution networks are exploited to distribute the global clock signal over an integrated circuit, and exhibit high immunity to process, voltage, and temperature (PVT) variations, while tolerating non-uniform switching and an unbalanced distribution of the clocked elements.…”

“…Several proposals for optimizing non-tree distribution networks have been presented, employing either customized meshes [1][2][3][4][5][6][7] or automating the process of adding crosslinks to the clock tree to enhance tolerance and lower power [8], [9]. Yet other papers propose removing some edges from a mesh to reduce power while minimally increasing the skew [10], [11].…”