Clocking design and analysis for a 600-MHz Alpha microprocessor

Bailey, Diana M.; Benschneider, B.J.

doi:10.1109/4.726547

Cited by 159 publications

(67 citation statements)

References 10 publications

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“…Furthermore, the clock skew time is not the same at the sender and the receiver. However, this difference is negligible when one considers that the clock skew time is tens of pico-seconds [25], whereas the one-way transmission delay is usually larger than milli-second order.…”

Section: Jtcp-methodsmentioning

confidence: 99%

Receiver-Based ACK Splitting Mechanism for TCP over Wired/Wireless Heterogeneous Networks

Hasegawa

Nakata

Nakano

2007

IEICE Transactions on Communications

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SUMMARYWith the rapid development of wireless network technologies, heterogeneous networks with wired and wireless links are becoming common. However, the performance of TCP data transmission deteriorates significantly when a TCP connection traverses such networks, mainly because of packet losses caused by the high bit error rate of wireless links. Many solutions for this problem have been proposed in the past literature. However, most of them have various drawbacks, such as difficulties in their deployment by the wireless access network provider and end users, violation of TCP's end-to-end principle by splitting the TCP connection, or inapplicability to IP-level encrypted traffic because the base station needs to access the TCP header. In this paper, we propose a new mechanism without such drawbacks to improve the performance of TCP over wired and wireless heterogeneous networks. Our mechanism employs a receiver-based approach, which does not need modifications to be made to the sender TCP or the base station. It uses the ACK-splitting method for increasing the congestion window size quickly in order to restrain the throughput degradation caused by packet losses due to the high bit error rate of wireless links. We evaluate the performance of our mechanism and show that our mechanism can increase throughput by up to 94% in a UMTS network. The simulation results also show that our mechanism does not significantly deteriorate even when the receiver cannot perfectly distinguish whether packet losses are due to network congestion or bit errors on the wireless links.

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Section: Jtcp-methodsmentioning

confidence: 99%

Receiver-Based ACK Splitting Mechanism for TCP over Wired/Wireless Heterogeneous Networks

Hasegawa

Nakata

Nakano

2007

IEICE Transactions on Communications

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“…The complexity is further increased in 3-D ICs as sequential elements belonging to the same clock domain (i.e., synchronized by the same clock signal) can be located on different planes. Another important issue in the design of clock distribution networks is low power consumption, since the clock network dissipates a significant portion of the total power consumed by a synchronous circuit [101], [102]. This demand is stricter for 3-D ICs due to the increased power density and related thermal limitations.…”

Section: Synchronization In 3-d Circuitsmentioning

confidence: 99%

Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits

2009

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“…FastHenry uses a standard filament discretization of an integral formulation of magnetoquasistatic coupling [29], [30]. The 3-D capacitance solver FastCap [22] was used to estimate the capacitance of the structure. In the capacitance model, conductors in upper and lower metal layers were represented, as they influence the capacitance of the clock structure.…”

Section: Minimizing Interconnect Self Inductancementioning

confidence: 99%

“…Finally, a supply voltage of 1.8 V was used in all the experiments. We used a distributed RLC model to model the interconnects where FastCap [22] was used to model the interconnect capacitance and FastHenry [23] was used to model both the resistance and the inductance of the interconnects. Both FastHenry and FastCap employ multipole-accelerated Method-of-Moments techniques [24], [25].…”

Section: Minimizing Coupling Inductancementioning

confidence: 99%

Expression of Concern: Managing on-chip inductive effects

Massoud

Majors²,

Kawa

et al. 2002

IEEE Trans. VLSI Syst.

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Abstract-With process technology and functional integration advancing steadily, chips are continuing to grow in area while critical dimensions are shrinking. This has led to the emergence of on-chip inductance to be a factor whose effect on performance and on signal integrity has to be managed by chip designers and has to be sometimes traded off against other performance parameters. In this paper, we cover several techniques to reduce on-chip inductance which in turn improve timing predictability and reduce signal delay and crosstalk noise. We present experimental results obtained from simulations of a typical high performance bus structure and a clock tree structure to examine the effectiveness of some of the different inductance reduction techniques.

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Clocking design and analysis for a 600-MHz Alpha microprocessor

Cited by 159 publications

References 10 publications

Receiver-Based ACK Splitting Mechanism for TCP over Wired/Wireless Heterogeneous Networks

Receiver-Based ACK Splitting Mechanism for TCP over Wired/Wireless Heterogeneous Networks

Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits

Expression of Concern: Managing on-chip inductive effects

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