Clocked control scheme of separating TFTs for a node‐sharing LTPS TFT shift register with large number of outputs

Abstract

This paper proposes the node-sharing low-temperature poly-silicon (LTPS) thin-film transistor (TFT) shift register with the clocked control scheme that completely turns separating TFTs off during the bootstrapping period to compensate for internal resistive and capacitive loads. The fluctuation is also addressed by adding pull-down TFTs or raising the low level of the control signal.

Review of Integrated Gate Driver Circuits in Active Matrix Thin-Film Transistor Display Panels

“…If there exist no overlaps between CLK1 and CLK2, the bootstrapping level without Q-sharing is not achievable by this simple Q-sharing architecture. To cope with this bootstrapping loss, a separating TFT (ST1) is placed between pulling-up TFTs of N6 and N8 as shown in Figure 15, where the shift register is designed at the backplane of n-type LTPS TFTs [92][93][94]. Because separating TFTs between pulling-up TFTs are turned off during the bootstrapping phase, the gate nodes (Q1, Q2) of pulling-up TFTs are fully boosted without any bootstrapping degradation caused by other pulling-up TFTs.…”

“…For 1/2, 1/4, and 1/8 resolution areas, 2, 4, and 8 lines are driven at the same time, respectively, resulting in the reduction on the effective number of lines by the same factors. The multi-line driving shift registers are implemented based on the Q-node sharing architecture described in Section 2.6 [92,93] and the output pulse sequences are adjusted by changing the timing of the clock signals [113]. Effective numbers of lines are reduced to 30.3 % and 21.0 % for 4,800 × 4,800 and 9,600 × 9,600 resolutions, respectively.…”

Variable Clock and EM Signal Generation Scheme for Foveation-Based Driving OLED Head-Mounted Displays

“…The previous foveation-based driving scheme is composed of vertical resolution reduction and multi-output driving gate circuit [22,23], as depicted in Figure 1, where the low-level gate pulses enable the pixel charging by assuming that the display panel is manufactured at a backplane of p-channel TFTs. The vertical resolution reduction curtails the vertical resolution of the input image with the much smaller number of lines by merging multiple-line pixels into one-line pixels with their average values in accordance with f RR .…”

Effectiveness of Electrical and Optical Detection at Pixel Circuit on Thin-Film Transistors

“…Thus, the paper investigated whether the defect characteristics are based on open, short, and cross short defects on the thin-film transistor pixel circuit. On the other hand, the TFT resolution moves forward to the high-definition [ 7 , 8 , 9 ] as the market requests a wide view illumination coupled to the ultra-high definition. The pixel circuit in TFT is trending toward smaller and smaller dimensions.…”