Circular BIST with state skipping

Abstract

Abstract-Circular built-in self-test (BIST) is a "test per clock" scheme that offers many advantages compared with conventional BIST approaches in terms of low area overhead, simple control logic, and easy insertion. However, it has seen limited use because it does not reliably provide high fault coverage. This paper presents a systematic approach for achieving high fault coverage with circular BIST. The basic idea is to add a small amount of logic that causes the circular chain to skip to particular states. This "state skipping" logic can be used to break out of limit cycles, break correlations in the test patterns, and jump to states that detect random-pattern-resistant faults. The state skipping logic is added in the chain interconnect and not in the functional logic, so no delay is added on system paths. Results indicate that in many cases, this approach can boost the fault coverage of circular BIST to match that of conventional parallel BIST approaches while still maintaining a significant advantage in terms of hardware overhead and control complexity. Results are also shown for combining "state skipping" logic with observation point insertion to further reduce hardware overhead.Index Terms-Built-in self-test (BIST), built-in testing, circuit testing, design for testability, limit cycles, pseudorandom pattern generation, scan chains.

Efficient LFSR Reseeding Based on Internal-Response Feedback

“…we give the average number of gate area overhead of the two schemes under different L CRP . Table 3 compares the gate area overhead and the test application time of the proposed internal-response-based reseeding method against the previous mixed-mode BIST methods, including the ROM-based reseeding schemes [6,7] and the mapping-logic-based schemes [15,19]. Since the previous work in [6,7] does not report gate area overhead, we estimate their gate area overhead based on the reported controller architectures and the reported number of required ROM bits.…”

“…Since the previous work in [6,7] does not report gate area overhead, we estimate their gate area overhead based on the reported controller architectures and the reported number of required ROM bits. In Table 3, we highlight the cases where our methods (L CRP = 100 or 400) uses smaller area overhead or shorter test application time than those in [6,7,15,19]. As can be seen, our Table 4 compares the results of the proposed method (with L CRP =100) and the work that generates patterns by feeding the circuit responses back to its inputs [5,12,13].…”

“…The circular self-test scheme [15,19] replaces each primary input and output with a special BIST cell and connects them together with internal scan cells to form a circular self-test path. Both pattern generation and signature analysis can be done using the self-test path, and thus only small area overhead is needed.…”

“…The results also show that when longer test time is allowed for one seed to generate more pseudo-random patterns, both the number of required internal nets and gate-area overhead can be further reduced. Compared to the ROM-based reseeding methods in [6,7] and the mapping-logic-based BIST in [15,19], the proposed method results in much smaller gate-area overhead and shorter test-application time in most cases.…”

“…Comparisons of proposed internal-response-based BIST and previous mixed mode BIST methods[6,7,15,19] Circuit Name Gate Area Overhead (A%) Test Application Time (#Cycles)…”