Efficient LFSR Reseeding Based on Internal-Response Feedback

Abstract

LFSR reseeding techniques are widely adopted in logic BIST to enhance fault detectability and shorten testapplication time for integrated circuits. In order to achieve complete fault coverage, previous reseeding methods often need a prohibitive amount of memory to store all required seeds. In this paper, a new LFSR reseeding technique is presented, which employs the responses of internal nets of the circuit itself as the control signals for changing LFSR states. A novel reseeding architecture containing a netselection logic module and an LFSR with some inversion logic is presented to generate all the required seeds on-chip in real time with no external or internal storage requirement. Experimental results on ISCAS and large ITC circuits show that the presented technique can achieve 100 % fault coverage with short test time by using only 0.23 -2.75 % of internal nets and with 2.35 -4.56 % gate area overhead on average for reseeding control without degrading the original circuit performance.

A Test-per-cycle BIST architecture with low area overhead and no storage requirement

“…1, the proposed BIST architecture consists of a MISR, a number of multiplexers (MUX) each of which provides one input to the MISR, an XOR-tree-based network, a net-selection logic unit and an on-chip BIST control unit. Similar to other test-per-clock BIST methods [5][6][7][8][9][10][11][12][13], we insert a scan cell for each primary input and connect them with the original scan cells of the circuit under test (CUT) to form the MISR such that the length of the MISR is equal to the sum of the numbers of primary inputs and pseudo-primary inputs to the CUT. For simplicity we will call this number as #PPI.…”

“…This XOR-tree compactor contains (#PPO -#CO) = (#PPO -#MUX + #OBP) 2-input XOR-gates. The area overhead of the XOR-tree-based network and the MISR in our scheme is much smaller than a conventional, separate response monitor in the test-per-clock scheme [5][6] [10][11][12][13].…”

“…The mixed-mode BIST technique [2][3][4][5][6] [10][11][12][13] employs both pseudo-random and deterministic patterns to achieve complete fault coverage in a short time, where the deterministic patterns can be stored in an on-chip ROM or provided from an external tester. Storing deterministic patterns in on-chip ROM reduces tester memory requirement and hence test equipment cost.…”

“…However the methods in [10][11] still require many sets of internal nets to generate all deterministic patterns. In [13] a new reseeding technique is proposed which employs the internal net responses as the control signals to generate required seeds. In this way, only a few internal nets are needed for complete fault coverage.…”

“…In general the BIST methods can be classified into test-perscan [2][3][4] and test-per-clock [5][6][7][8][9][10][11][12][13] methods according to their test application schemes. The test-per-scan method serially loads each test pattern into scan chains bit-by-bit.…”