A Test-per-cycle BIST architecture with low area overhead and no storage requirement

Shiao, Chung-Min; Lien, Wei-Cheng; Lee, Kuen-Jong

doi:10.1109/vlsi-dat.2016.7482556

Cited by 10 publications

(6 citation statements)

References 10 publications

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“…The simplest approach to test stuck-at faults in digital combinational circuits is to use an exhaustive test pattern generation, where the test set comprises of all the possible input combinations (input space) [1][2][3][4][5][6][7][8][9][10]. For an N-input circuit under test, it requires test patterns to achieve complete fault coverage.…”

Section: Introductionmentioning

confidence: 99%

Adaptive random testing with total cartesian distance for black box circuit under test

Alamgir

A’ain

Paraman

et al. 2020

IJEECS

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<p>Testing and verification of digital circuits is of vital importance in electronics industry. Moreover, key designs require preservation of their intellectual property that might restrict access to the internal structure of circuit under test. Random testing is a classical solution to black box testing as it generates test patterns without using the structural implementation of the circuit under test. However, random testing ignores the importance of previously applied test patterns while generating subsequent test patterns. An improvement to random testing is Antirandom that diversifies every subsequent test pattern in the test sequence. Whereas, computational intensive process of distance calculation restricts its scalability for large input circuit under test. Fixed sized candidate set adaptive random testing uses predetermined number of patterns for distance calculations to avoid computational complexity. A combination of max-min distance with previously executed patterns is carried out for each test pattern candidate. However, the reduction in computational complexity reduces the effectiveness of test set in terms of fault coverage. This paper uses a total cartesian distance based approach on fixed sized candidate set to enhance diversity in test sequence. The proposed approach has a two way effect on the test pattern generation as it lowers the computational intensity along with enhancement in the fault coverage. Fault simulation results on ISCAS’85 and ISCAS’89 benchmark circuits show that fault coverage of the proposed method increases up to 20.22% compared to previous method.</p>

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Section: Introductionmentioning

confidence: 99%

Adaptive random testing with total cartesian distance for black box circuit under test

Alamgir

A’ain

Paraman

et al. 2020

IJEECS

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“…Speedy testing even throughout the production cycle is not sufficient to maintain modern reliability standards [8]. Therefore, high performance embedded systems are equipped with highly reliable built-in self-test (BIST) for an on-chip testing during normal operations [9][10][11][12][13][14]. Comprising of test pattern generator and output response analyzer within the system, BIST automatically generates test patterns and compares the fault-free responses [10][11][12][13]15].…”

Section: Introductionmentioning

confidence: 99%

“…BIST uses pseudorandom test pattern generation (PRTG) through linear feedback shift register (LFSR) because of its simplicity and cost effectiveness [3,9,[11][12][13][16][17][18]. PRTG outperforms other black-box test pattern generation approaches with its ability to generate large number of random test patterns irrespective of the structural implementation of circuit under test (CUT) [19].…”

Section: Introductionmentioning

confidence: 99%

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Horizontal diversity in test generation for high fault coverage

Alamgir¹,

A’ain²,

Paraman³

et al. 2018

Turk J Elec Eng & Comp Sci

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Determination of the most appropriate test set is critical for high fault coverage in testing of digital integrated circuits. Among black-box approaches, random testing is popular due to its simplicity and cost effectiveness. An extension to random testing is antirandom that improves fault detection by maximizing the distance of every subsequent test pattern from the set of previously applied test patterns. Antirandom testing uses total Hamming distance and total cartesian distance as distance metrics to maximize diversity in the testing sequence. However, the algorithm for the antirandom test set generation has two major issues. Firstly, there is no selection criteria defined when more than one test pattern candidates have the same maximum total Hamming distance and total cartesian distance. Secondly, determination of total Hamming distance and total Cartesian distance is computational intensive as it is a summation of individual Hamming distances and cartesian distances with all the previously selected test patterns. In this paper, two-dimensional Hamming distance is proposed to address the first issue. A novel concept of horizontal Hamming distance is introduced, which acts as a third criterion for test pattern selection. Fault simulations on ISCAS'85 and ISCAS'89 benchmark circuits have shown that employing horizontal Hamming distance improves the effectiveness of pure antirandom in terms of fault coverage. Additionally, an alternative method for total Hamming distance calculations is proposed to reduce the computational intensity. The proposed method avoids summation of individual Hamming distances by keeping track of number of 0s and 1s applied at each inputs. As a result, up to 90% of the computations are reduced.

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“…However, because of the existence of pseudo-random pattern resistant faults, it is difficult to achieve a satisfactory fault coverage in a limited cycling. [8] achieves test-per-clock test without data storage by adopting LFSR reseeding and test point insertion. [9] proposed a efficiently deterministic test-per-clock test using LFSR-reseeding and TVAC technologies.…”

Section: Introductionmentioning

confidence: 99%

An efficient controlled LFSR hybrid BIST scheme

Liu

2018

IEICE Electron. Express

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A new hybrid built-in self-test (BIST) test scheme is proposed. The test scheme consists of two components: the free LFSR mode (pseudorandom test) and the controlled LFSR mode (deterministic test). In order to improve the test quality of pseudo-random test sequence, a forward-backward pseudo-random test generation method is proposed. As every shifted-in bit is fully used to generate the most efficient test and the ratio of do not care bits is maximized in the remaining test pattern repository, the proposed controlled LFSR test generation method can find the targeted pattern with the minimal number of shift, efficiently embedding the deterministic test set into test-per-clock stream. Simulation results demonstrate that the proposed method considering for layout constraints shows great advantages in test data storage and test application time compared with previous methods.

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A Test-per-cycle BIST architecture with low area overhead and no storage requirement

Cited by 10 publications

References 10 publications

Adaptive random testing with total cartesian distance for black box circuit under test

Adaptive random testing with total cartesian distance for black box circuit under test

Horizontal diversity in test generation for high fault coverage

An efficient controlled LFSR hybrid BIST scheme

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