Horizontal diversity in test generation for high fault coverage

Abstract

Determination of the most appropriate test set is critical for high fault coverage in testing of digital integrated circuits. Among black-box approaches, random testing is popular due to its simplicity and cost effectiveness. An extension to random testing is antirandom that improves fault detection by maximizing the distance of every subsequent test pattern from the set of previously applied test patterns. Antirandom testing uses total Hamming distance and total cartesian distance as distance metrics to maximize diversity in the testing sequence. However, the algorithm for the antirandom test set generation has two major issues. Firstly, there is no selection criteria defined when more than one test pattern candidates have the same maximum total Hamming distance and total cartesian distance. Secondly, determination of total Hamming distance and total Cartesian distance is computational intensive as it is a summation of individual Hamming distances and cartesian distances with all the previously selected test patterns. In this paper, two-dimensional Hamming distance is proposed to address the first issue. A novel concept of horizontal Hamming distance is introduced, which acts as a third criterion for test pattern selection. Fault simulations on ISCAS'85 and ISCAS'89 benchmark circuits have shown that employing horizontal Hamming distance improves the effectiveness of pure antirandom in terms of fault coverage. Additionally, an alternative method for total Hamming distance calculations is proposed to reduce the computational intensity. The proposed method avoids summation of individual Hamming distances by keeping track of number of 0s and 1s applied at each inputs. As a result, up to 90% of the computations are reduced.

Adaptive random testing with total cartesian distance for black box circuit under test

“…Testing sequence is a collection of test patterns represented by T. As shown in (1) and (2) report definitions for CD and TCD. These definitions are true for testing sequence and test pattern where for an N-input circuit under test [1,2,7,8,10,11,18,20,27,28].…”

“…The simplest approach to test stuck-at faults in digital combinational circuits is to use an exhaustive test pattern generation, where the test set comprises of all the possible input combinations (input space) [1][2][3][4][5][6][7][8][9][10]. For an N-input circuit under test, it requires test patterns to achieve complete fault coverage.…”

“…Consequently, a candidate with maximum of the minimum distances is selected. All these algorithms successfully reduce the computational complexity at the cost of compromised fault coverage [1,2,7,8,10,27,28].…”

Multiple Controlled Antirandom Testing (MCAT) for High Fault Coverage in a Black Box Environment

“…Regardless of the structural implementation, Random testing generates random test patterns using the information of primary inputs of circuit under test. However, besides abstaining the structural implementation, Random testing neglects the significance of the previously executed test patterns while generating subsequent test patterns [10]- [16]. A Lack of guidance from success or failure rate of previously executed test patterns may lead to generation of redundant test patterns [5], [17].…”