Circuit reliability

As CMOS devices become smaller, process variations-induced uncertainty imposes a large spread in the circuit timing and therefore, it becomes one of the main issues for circuit yield. To analyse/optimise the timing of the circuit under process variation effects, statistical analysis/optimisation techniques are more suitable than the traditional static analysis/ optimisation counterparts. Statistical gate sizing is an effective technique that is widely used to guide the timing yield improvement of digital circuits. Gate criticality, defined as the probability that a gate lies on a critical path, forms the basis for many of the existing statistical gate sizing techniques. Here, the authors introduce adjacency criticality to address the drawbacks of the conventional definition of gate criticality. It is defined as the probability of manufacturing a chip in which the gate lies on the critical path due to process variation considering the effect of the gates in its fan-out cone. Furthermore, the authors present the levelised Adjacency Criticality metric which provides a trade-off between the runtime of the criticality metric and accuracy of the Adjacency Criticality metric. In order to show the efficacy of the proposed metric, an adjacency criticalitybased statistical gate sizing method is presented for improving timing yield of the circuit.

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Extending standard cell library for aging mitigation

Kiamehr¹,

Ebrahimi²,

Firouzi³

et al. 2015

IET Computers & Digital Techniques

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Transistor aging, mostly due to bias temperature instability (BTI), is one of the major unreliability sources at nano-scale technology nodes. BTI causes the circuit delay to increase and eventually leads to a decrease in the circuit lifetime. Typically, standard cells in the library are optimised according to the design time delay; however, because of the asymmetric effect of BTI, the rise and fall delays might become significantly imbalanced over the lifetime. In this study, the BTI effect is mitigated by balancing the rise and fall delays of the standard cells at the excepted lifetime. The authors find an optimal tradeoff between the increase in the library size and the lifetime improvement by non-uniform extension of the library cells for various ranges of the input signal probabilities. The simulation results reveal that this technique can prolong the circuit lifetime by around 150% with a negligible area overhead. Moreover, the effect of different realistic workloads on the distribution of internal node signal probabilities is investigated. This is done to obtain the sensitivity of the proposed static (design time) approach to different workloads during system lifetime. The results show that the proposed approach is still efficient if the workload changes during the runtime.

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Circuit reliability

Cited by 11 publications

References 50 publications

Aging-Aware Standard Cell Library Optimization Methods

Aging-Aware Standard Cell Library Optimization Methods

Adjacency criticality: a simple yet effective metric for statistical timing yield optimisation of digital integrated circuits

Extending standard cell library for aging mitigation

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