Circuit-level simulation of CDM-ESD and EOS in submicron MOS devices

Study of CDM specific effects for a smart power input protection structure

“…In previous results [1][2][3][4][5][6][7], CDM simulation has been used to reconstruct failures in ICs after CDM stress had been applied. The substrate has not been considered for the simulations.…”

“…Most authors put the emphasis on modeling the behavior of ESD protection structures [2][3][4]6], including MOS snapback. Other works focus on simulating the behavior of test circuits and input/output structures during CDM stress [1,5,6] or determination of the behavior of complete ICs [7].…”

“…In the past, various simulation and modeling approaches have been reported for CDM circuit simulation [1][2][3][4][5][6][7]. Most authors put the emphasis on modeling the behavior of ESD protection structures [2][3][4]6], including MOS snapback.…”

Compact distributed multi-finger MOSFET model for circuit-level ESD simulation

“…Transistors exposed to ESD include those used in I/O circuits and active rail clamp circuits. Many ESDrelevant models for MOSFETs may be found in the open literature, e.g., [6][7][8][9][10][11][12][13][14][15][16][17][18][19][20]. The majority of these works treat the body resistance as a single element, in effect representing the device as a single-finger MOSFET.…”

Verification of CDM circuit simulation using an ESD evaluation circuit

“…Hence, research in the past has dealt with the ability to determine the behavior of ICs during CDM discharges with circuit simulation. Several studies investigate CDM behavior on device level [1][2][3][4] and for input circuits and test structures [4][5][6][7]. Addressing chip level simulation of CDM discharges, Lee et al [8] suggest that the probability of gate oxide rupture is correlated with the package capacitance of connected circuit parts.…”