Choices of operand truncation in the SRT division algorithm

Burgess, Neil; Williams, Ted E.

doi:10.1109/12.392852

Cited by 16 publications

(6 citation statements)

References 17 publications

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“…The allowable choices of , , and determined in this study correspond with the results presented in [4] for radix 8 and 16. In our study, we extend the allowed operand truncations to radix 32.…”

Section: B Higher Radixmentioning

confidence: 87%

“…In order for the next partial remainder to be bounded, the value of the quotient-digit is chosen such that divisor (4) The final quotient is the weighted sum of all of the quotientdigits selected throughout the iterations, such that:…”

Section: A Recurrencementioning

confidence: 99%

“…Burgess and Williams [4] present in more detail allowable truncations for divisors and both carry-save and borrow-save partial remainders. However, a more detailed comparison of quotient-digit selection complexity between different designs requires more information than input precision.…”

Section: Introductionmentioning

confidence: 99%

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Minimizing the complexity of SRT tables

Oberman

Flynn

1998

IEEE Trans. VLSI Syst.

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This paper presents an analysis of the complexity of quotient-digit selection tables in SRT division implementations. SRT dividers are widely used in VLSI systems to compute floating-point quotients. These dividers use a fixed number of partial remainder and divisor bits to consult a table to select the next quotient-digit in each iteration. This analysis derives the allowable divisor and partial remainder truncations for radix 2 through radix 32, and it quantifies the relationship between table parameters and the complexity of the tables. Several techniques are presented for further minimizing table complexity. By mapping the tables to a library of standard-cells, delay and area values were measured and are presented for table configurations through radix 32. Several conclusions are drawn based on this data which impacts optimized SRT divider designs.

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Section: B Higher Radixmentioning

confidence: 87%

Section: A Recurrencementioning

confidence: 99%

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Minimizing the complexity of SRT tables

Oberman

Flynn

1998

IEEE Trans. VLSI Syst.

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“…Many works are going on to provide different standpoints for high-radix dividers. Use of different look-up tables along with quotient-digit selection logic look-up table [39][40][41], speculating quotient digit and using arithmetic functions to multiplicative iterations rather than subtractive iterations [42], pre-scaling operands [43][44][45], using Fourier division [46,47], using alternative digit codes such as binary-coded decimal (BCD) digits instead of decimal and basic binary digits [48], cascading multiple stages of lower radix dividers [49], overlapping two or more stages of low radix [50,51], a truncated schema of exact cell binary shifted adder array [52][53][54], on-line serial and pipelined operand division [55], parallel implementation of the low-radix dividers [8], array implementation [56], these are some of the possible ways applicable for high-radix dividers.…”

Section: Predict-correct Algorithm For Divisionmentioning

confidence: 99%

Low-Latency Bit-Accurate Architecture for Configurable Precision Floating-Point Division

Xia

Liu

et al. 2021

Applied Sciences

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Floating-point division is indispensable and becoming increasingly important in many modern applications. To improve speed performance of floating-point division in actual microprocessors, this paper proposes a low-latency architecture with a multi-precision architecture for floating-point division which will meet the IEEE-754 standard. There are three parts in the floating-point division design: pre-configuration, mantissa division, and quotient normalization. In the part of mantissa division, based on the fast division algorithm, a Predict–Correct algorithm is employed which brings about more partial quotient bits per cycle without consuming too much circuit area. Detailed analysis is presented to support the guaranteed accuracy per cycle with no restriction to specific parameters. In the synthesis using TSMC, 90 nm standard cell library, the results show that the proposed architecture has ≈63.6% latency, ≈30.23% total time (latency × period), ≈31.8% total energy (power × latency × period), and ≈44.6% efficient average energy (power × latency × period/efficient length) overhead over the latest floating-point division structure. In terms of latency, the proposed division architecture is much faster than several classic processors.

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“…Extensive literature exists describing the theory of division. Subtractive methods, such as nonrestoring SRT division which was independently proposed by and subsequently named for Sweeney, Robertson, and Tocher, are described in detail in [3], [4], [7], [17], [21], [22]. Multiplication-based algorithms such as functional iteration are presented in [1], [9], [11], [23].…”

Section: Introductionmentioning

confidence: 99%

Design issues in division and other floating-point operations

Oberman

Flynn

1997

IEEE Trans. Comput.

144

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Floating-point division is generally regarded as a low frequency, high latency operation in typical floating-point applications. However, in the worst case, a high latency hardware floating-point divider can contribute an additional 0.50 CPI to a system executing SPECfp92 applications. This paper presents the system performance impact of floating-point division latency for varying instruction issue rates. It also examines the performance implications of shared multiplication hardware, shared square root, on-the-fly rounding and conversion, and fused functional units. Using a system level study as a basis, it is shown how typical floating-point applications can guide the designer in making implementation decisions and trade-offs.

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Choices of operand truncation in the SRT division algorithm

Cited by 16 publications

References 17 publications

Minimizing the complexity of SRT tables

Minimizing the complexity of SRT tables

Low-Latency Bit-Accurate Architecture for Configurable Precision Floating-Point Division

Design issues in division and other floating-point operations

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