Minimizing the complexity of SRT tables

Abstract

This paper presents an analysis of the complexity of quotient-digit selection tables in SRT division implementations. SRT dividers are widely used in VLSI systems to compute floating-point quotients. These dividers use a fixed number of partial remainder and divisor bits to consult a table to select the next quotient-digit in each iteration. This analysis derives the allowable divisor and partial remainder truncations for radix 2 through radix 32, and it quantifies the relationship between table parameters and the complexity of the tables. Several techniques are presented for further minimizing table complexity. By mapping the tables to a library of standard-cells, delay and area values were measured and are presented for table configurations through radix 32. Several conclusions are drawn based on this data which impacts optimized SRT divider designs.

Low‐Latency SRT Division and Square Root Based on Remainder and Quotient Prediction

“…In Refs. [16,17], they implemented high radix by enlarging lookup table and increasing adders, but the overhead grows rapidly [6] .…”

“…Combining division and square root based on Sweeney, Robertson and Tocher algorithm (SRT) is widely used in processors. Intel Pentium CPUs [3] , ARM processors [4] and IBM FPUs [5] use SRT4 and Intel Core2 [6] uses SRT16 to implement the two operations.…”

“…Pipeline can achieve high throughput, while much extra hardware cost is consumed. Some researchers proposed to imple-ment high radix SRT by enlarging lookup table and increasing adders which lead to the table delay increasing linearly and the area increasing quadratically [6] .…”

Design issues in division and other floating-point operations

“…Extensive literature exists describing the theory of division. Subtractive methods, such as nonrestoring SRT division which was independently proposed by and subsequently named for Sweeney, Robertson, and Tocher, are described in detail in [3], [4], [7], [17], [21], [22]. Multiplication-based algorithms such as functional iteration are presented in [1], [9], [11], [23].…”

High throughput divider using output prediction logic

“…Various techniques have been proposed to improve the latency of a high radix divider, including 1) minimizing the quotient look-up-table for high radix SRT implementations [2]; 2) replication of simple radix-2 stages and overlapping sections of one stage with another stage [3]; and 3) first computing two possible partial remainders while calculating the correct quotient fraction, then updating the partial remainder with the correct quotient fraction [4]. All of these methods are based on the principle of repetitively utilizing one dividing unit until all quotient fractions are generated.…”