Chip to wafer copper direct bonding electrical characterization and thermal cycling

Beilliard, Yann; Coudrain, P.; Cioccio, L. Di; Moreau, S.; Sanchez, L.; Montmayeul, Brigitte; Signamarcheix, T.; Estevez, Rafaël; Parry, Guillaume

doi:10.1109/3dic.2013.6702315

Cited by 12 publications

(1 citation statement)

References 9 publications

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“…This technology, based on almost standard CMP process, does not require any pressure and no temperature -No underfill is needed neither. If this technology is under development since several years and near of industrialization on a Wafer-To-Wafer approach, some advanced work on Chip-To-Wafer is also under work, making this promising process compatible with interposer [14]. Crosse section of a pad stacked thanks to copper-copper direct bonding is shown on figure 8.…”

Section: B Technology and Integrationmentioning

confidence: 99%

3D advanced integration technology for heterogeneous systems

Vivet

Bernard

Clermidy

et al. 2015

2015 International 3D Systems Integration Conference (3DIC)

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International audience3D integration technology is nowadays mature enough, offering today further system integration using heterogeneous technologies, with already many different industrial successes (Imagers, 2.5D Interposers, 3D Memory Cube, etc.). CEA-LETI has been developing for a decade 3D integration, and have pursued research in both directions: developing advanced 3D technology bricks (TSVs, µ-bumps, Hybrid Bonding, etc), and designing advanced 3D circuits as pioneer prototypes. In this paper, a short overview of some recent advanced 3D technology results is presented, including some latest 3D circuit's description

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Section: B Technology and Integrationmentioning

confidence: 99%