Chip-To-Package Interconnections

Totta, P. A.; Khadpe, Subash; Koopman, N.G.; Reiley, T.C.; Sheaffer, Michael J.

doi:10.1007/978-1-4615-6037-1_2

Cited by 30 publications

(4 citation statements)

References 63 publications

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“…The high-performance stacked EDRAM cache prototype (Figure 8a) was built using more than 11,000 TSVs. Strata-1 and 2 emulate stacked processor and cache respectively as described in [5]. Memory functionality and strata-to-strata communication were tested using the built-in-self-test engine (BIST) on each strata.…”

Section: Hardware Resultsmentioning

confidence: 99%

“…There are various methods for achieving the formation of the metallic protrusions that can be used for this. The well-known method of using C4 interconnects, typically used in chip packaging, is not suitable for multiple wafer stacking due to thermal budget limitations and the large size of C4s, which limits bandwidth [5]. Therefore, alternative methods have been considered, as described below.…”

Section: Metal-metal Bondingmentioning

confidence: 99%

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Three-Dimensional Wafer Stacking Using Cu TSV Integrated with 45 nm High Performance SOI-CMOS Embedded DRAM Technology

Batra

Skordas

LaTulipe

et al. 2014

JLPEA

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Section: Hardware Resultsmentioning

confidence: 99%

Section: Metal-metal Bondingmentioning

confidence: 99%

Three-Dimensional Wafer Stacking Using Cu TSV Integrated with 45 nm High Performance SOI-CMOS Embedded DRAM Technology

Batra

Skordas

LaTulipe

et al. 2014

JLPEA

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“…Flip-chip interconnect results in very short connect length and greatly reduces interconnect inductance and resistance [1], [2]. This technology can support a large number of input/output (I/O) pins because of the small solder joint size.…”

Section: Introductionmentioning

confidence: 99%

40μm Ag-AgIn flip-chip interconnect process at 180°C

Lin

Sha

Lee

2012

2012 IEEE 62nd Electronic Components and Technology Conference

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40μm silver-silver indium (Ag-AgIn) flip-chip interconnect process at 180ºC by transient liquid phase (TLP) bonding process is reported. Array of 50x50 flip-chip joints with 100μm pitch and 40μm joint diameter was fabricated on silicon (Si) and bonded to copper (Cu) substrate at 180℃ for 5 minutes with a static pressure of 0.4-0.7MPa (60-100psi). The corresponding load for each joint is 0.05gm. In the bonding, no flux was used. Cross section SEM images show that Ag columns are well bonded to the Cu substrate without visible voids or cracks. EDX data indicate that the resulting column structure is Ag/(Ag)/Ag 2 In/(Ag). Each joint has height approximately 50μm. In this structure, Ag 2 In is a dominating intermetallic compound (IMC) in the Ag-In system with melting temperature of 660ºC. (Ag) is a solid solution phase of Ag with In composition up to 20 at. %. It has a solidus temperature range of 695 to 962ºC depending on In composition. In long-term operation, (Ag)/Ag 2 In/(Ag) is expected to gradually convert to a single (Ag) phase which is more reliable. Thus, the flip-chip joints will get better in use. The process temperature of this new interconnect method is 80°C below typical reflow temperature of tin-based leadfree solders. The free shear strain of this 50μm Ag-AgIn flipchip interconnect between Si and Cu is around 0.14. This strain value is relatively small for ductile material such as Ag.

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“…The advantages of organic modules are mainly cost and matched coefficient of thermal expansion (CTE) to the card to which it ultimately must be attached. Flip-chip technology has also been known for quite a while as a packaging method with high input/output (I/O) capabilities [1]. Relatively recently, organic modules have been used for flip-chip applications.…”

Section: Introductionmentioning

confidence: 99%

Adhesion issues in flip-chip on organic modules

Tran¹,

Questad²,

Sammakia

1999

IEEE Trans. Comp. Packag. Technol.

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Flip chip attach on organic carriers is a novel electronic packaging assembly method which provides advantages of high input/output (I/O) counts, electrical performance and thermal dissipation. In this structure, the flip chip device is attached to organic laminate with predeposited eutectic solder. Mechanical coupling of the chip and the laminate is done via underfill encapsulant materials. As the chip size increases, the thermal mismatch between silicon and its organic carrier becomes greater. Adhesion becomes an important factor since the C4 joints fail quickly if delamination of the underfill from either chip or the solder mask interface occurs. Newly developed underfills have been studied to examine their properties, including interfacial adhesion strength, flow characteristics, void formation and cure kinetics. This paper will describe basic investigations into the properties of these underfills and also how these properties related to the overall development process.In addition, experiments were performed to determine the effects on adhesion degradation of flip chip assembly processes and materials such as IR reflow profile, flux quantity and residues. Surface treatment of both the chip and the laminate prior to encapsulation were studied to enhance underfill adhesion. Accelerated thermal cycling and highly accelerated stress testing (HAST) were conducted to compare various underfill properties and reliability responses.Index Terms-Chip carrier, electronic package, fracture toughness, interfacial delamination, underfill adhesive.

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Chip-To-Package Interconnections

Cited by 30 publications

References 63 publications

Three-Dimensional Wafer Stacking Using Cu TSV Integrated with 45 nm High Performance SOI-CMOS Embedded DRAM Technology

Three-Dimensional Wafer Stacking Using Cu TSV Integrated with 45 nm High Performance SOI-CMOS Embedded DRAM Technology

40μm Ag-AgIn flip-chip interconnect process at 180°C

Adhesion issues in flip-chip on organic modules

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Chip-To-Package Interconnections

Cited by 30 publications

References 63 publications

Three-Dimensional Wafer Stacking Using Cu TSV Integrated with 45 nm High Performance SOI-CMOS Embedded DRAM Technology

Three-Dimensional Wafer Stacking Using Cu TSV Integrated with 45 nm High Performance SOI-CMOS Embedded DRAM Technology

40&#x03BC;m Ag-AgIn flip-chip interconnect process at 180&#x00B0;C

Adhesion issues in flip-chip on organic modules

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40μm Ag-AgIn flip-chip interconnect process at 180°C