1999 4th International Symposium on Plasma Process-Induced Damage (IEEE Cat. No.99TH8395)
DOI: 10.1109/ppid.1999.798844
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Charging protection and degradation by antenna environment on NMOS and PMOS transistors

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Cited by 6 publications
(9 citation statements)
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“…This is also consistent with literature reports that charging impacts are more significant on pMOS than on nMOS devices [13], [19]- [21]. Although electron shading effect [22] is a well-known cause for the plasma damage susceptibility of pMOS antenna devices, because the shaded electrons lead to positive stressing of the gate dielectric, which corresponds to carrier accumulation of pMOS devices [20], [21]. However, in this work, electron shading effect is ruled out, since our antenna devices are with low aspect ratio and no dense-line antenna is used (i.e., area-intensive antenna only).…”
Section: ) Gate Leakage Current Measurementssupporting
confidence: 93%
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“…This is also consistent with literature reports that charging impacts are more significant on pMOS than on nMOS devices [13], [19]- [21]. Although electron shading effect [22] is a well-known cause for the plasma damage susceptibility of pMOS antenna devices, because the shaded electrons lead to positive stressing of the gate dielectric, which corresponds to carrier accumulation of pMOS devices [20], [21]. However, in this work, electron shading effect is ruled out, since our antenna devices are with low aspect ratio and no dense-line antenna is used (i.e., area-intensive antenna only).…”
Section: ) Gate Leakage Current Measurementssupporting
confidence: 93%
“…Moreover, pMOS devices are shown to be more vulnerable to charging damage since the leakage current of pMOS antenna devices are much larger than that of nMOS devices. This is also consistent with literature reports that charging impacts are more significant on pMOS than on nMOS devices [13], [19]- [21]. Although electron shading effect [22] is a well-known cause for the plasma damage susceptibility of pMOS antenna devices, because the shaded electrons lead to positive stressing of the gate dielectric, which corresponds to carrier accumulation of pMOS devices [20], [21].…”
Section: ) Gate Leakage Current Measurementssupporting
confidence: 90%
“…As mentioned below, recent studies showed that the interconnect connected to the active area even in some cases induces PCD. 14,23,24,57,58) Furthermore, it is expected that the effect of the width of the wiring interconnect on the antenna ratio -the difference in the width in terms of the wiring layers such as local, semi-global, and global interconnects -may be considered. However, owing to the stochastic phenomena for N ) 1 [some transistors are connected to wires in the global layers (larger r), and others, to the lower layer (smaller r) and vice versa], we can employ the overall trend of the r dependence in accordance with Rent's rule as a case study.…”
Section: Appendix Bmentioning
confidence: 99%
“…[15][16][17][18][19] The damage is usually quantified by measuring the gate leakage current increase 16,17) and threshold voltage shift (ÁV th ). 15,19) Since this charging damage is considered to be inevitable in present-day plasma equipment, antenna design rules that limit the maximum antenna ratio in circuits [20][21][22] and protection diode schemes 13,14,20,[23][24][25][26] have been introduced to minimize the damage. Although various protection diodes have been proposed and introduced into the circuit, the ability to suppress charging damage is believed to be structure-and process-dependent.…”
Section: Introductionmentioning
confidence: 99%
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