Charge trapping effects and interface state generation in a 40 V lateral resurf pDMOS transistor

Moens, P.; bosch, G. Van den; Wojciechowski, D.; Bauwens, F.; Vleeschouwer, Herbert De; Pestel, F. De

doi:10.1109/essder.2005.1546671

Cited by 11 publications

(2 citation statements)

References 7 publications

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“…2, it can be seen that the I dlin increases fast at the early stress stage, and then it tends to saturate after the stressing time of 2000s. The characteristic at the early time is similar to the degradation under dc stress condition [9]. On this occasion, the impact ionization center is located at the accumulation region (X = 10 − 12 μm), as shown in Fig.…”

Section: Measurements and Discussionmentioning

confidence: 83%

Linear Drain Current Degradation of FG-pLEDMOS Transistor Under Pulse Gate Stress With Different Rising and Falling Edges

Qian

Huang

Liu

et al. 2014

IEEE Trans. Device Mater. Relib.

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Linear drain current degradation of a field-gate p-channel lateral extended drain MOS (FG-pLEDMOS) transistor for different ac hot-carrier stress conditions has been experimentally investigated in this paper. It is noted that hot-carrier degradation strongly depends on the time of the rising and falling edges of the gate signal pulse. Faster rising and falling edges of the gate pulse will induce more serious hot-carrier degradation. Moreover, the experimental results reveal that the falling edges of the gate pulse show more distinct influence upon hot-carrier degradation than that of the rising edges. In this way, the pulse gate stress with fast falling edges should be considered for evaluating the hot-carrier-induced lifetime of a laterally diffused MOS working with fast gate signal pulse edges.Index Terms-Hot-carrier degradation, AC stress condition, field-gate p-channel lateral extended drain MOS (FG-pLEDMOS).

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Section: Measurements and Discussionmentioning

confidence: 83%

Linear Drain Current Degradation of FG-pLEDMOS Transistor Under Pulse Gate Stress With Different Rising and Falling Edges

Qian

Huang

Liu

et al. 2014

IEEE Trans. Device Mater. Relib.

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“…When the pLEDMOS is in the on-state, the gate of the highvoltage pLDMOS is always set to 0 V, but the source voltage is high (100 V), so the voltage between the gate and source is very high and the gate oxide of the pLEDMOS must be thicker than that of the standard CMOS devices. For being stressed under such a high electric field continuously, carriers can gain enough energy to surpass the Si/SiO 2 barrier, and can easily be trapped in the thick gate oxide and field oxide, or create interface states [4][5][6], altering the transistor's performance. Thus an in-depth understanding of the behavior of the devices upon hot-carrier stress is mandatory, and some modification and optimization must be done in the device structure.…”

Section: Study and Optimization Of Hot-carrier Degradationmentioning

confidence: 99%

Reliability investigations and improvements of the pLEDMOS for PDP data driver ICs

Qian¹,

Sun

Li³

et al. 2011

Semicond. Sci. Technol.

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In this paper, the p-type lateral extended drain MOS (pLEDMOS) transistor with thick gate oxide for plasma display panel (PDP) data driver ICs is developed. The following reliability issues have been discussed in detail: (1) hot-carrier degradation, (2) the contradiction between the parasitic bipolar junction transistor (BJT) punch-through phenomenon and the impurity segregation effect, (3) surface damage caused by the long-time diffusion process under high-temperature conditions, (4) creep behavior of the breakdown voltage and ( 5) the Kirk effect due to the high working current density. The improved methods for solving these reliability problems by optimizing the process and device architecture are also presented. The methods have also been verified by the technology computer-aided design (TCAD) simulations and experimental results.

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The degradation mechanisms in high voltage pLEDMOS transistor with thick gate oxide

Wang¹,

Sun²,

Yi³

et al. 2008

Microelectronics Reliability

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Charge trapping effects and interface state generation in a 40 V lateral resurf pDMOS transistor

Cited by 11 publications

References 7 publications

Linear Drain Current Degradation of FG-pLEDMOS Transistor Under Pulse Gate Stress With Different Rising and Falling Edges

Linear Drain Current Degradation of FG-pLEDMOS Transistor Under Pulse Gate Stress With Different Rising and Falling Edges

Reliability investigations and improvements of the pLEDMOS for PDP data driver ICs

The degradation mechanisms in high voltage pLEDMOS transistor with thick gate oxide

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