Charge plasma technique based dopingless accumulation mode junctionless cylindrical surrounding gate MOSFET: analog performance improvement

Trivedi, Nitin; Kumar, Manoj; Haldar, Subhasis; Deswal, S. S.; Gupta, Mridula; Gupta, Rajeev

doi:10.1007/s00339-017-1176-y

Cited by 20 publications

(6 citation statements)

References 20 publications

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“…The Ox.schro model is considered for wave-function penetration in the oxide region and the CVT model is considered for the transverse field, doping dependent and temperature-dependent parts of the mobility. In the absence of an experimental report on charge plasma-based nanowire FETs, we calibrated our simulation parameters with the I d -V g characteristics curve reported by Trivedi et al [18]. Figure 2(a) depicts the transfer curves of the CCPNWT and the charge plasma-based accumulation mode nanowire transistor (CPANWT) at the same device dimension, and it can be seen that the I d -V g characteristics curve is quite comparable to the reported result [18].…”

Section: Device Structure and Methodologymentioning

confidence: 99%

“…The transconductance g m is defined as g m = δI d /δV g which measures how well a device converts voltage to current [8,18]. So, a higher transconductance value is desirable for analog applications.…”

Section: Analog/rf Performancementioning

confidence: 99%

“…So, the charge plasma-based device removes the requirements of the ultra-sharp doping profile providing a low thermal budget by simplifying manufacturing procedures and minimizes the influence of RDF. In recent years, it has been reported in many papers that the charge-plasma (CP)-based JL devices show better performance in terms of SCEs, and the variation of the SCEs parameter is also less than that of a conventional junctionless nanowire transistor (JLNWT) [18,19]. For further improvement of SCEs in junctionless devices, many researchers have proposed different gate-oxide engineering techniques, such 3.9 3.9 3.9…”

Section: Introductionmentioning

confidence: 99%

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Comparative analysis of gate-oxide engineering in charge plasma based nanowire transistor

Debnath,

Sikder,

Singha

2023

Eng. Res. Express

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In this work, a Hetero-Gate-Oxide Charge Plasma-based Nanowire Transistor (HGO-CPNWT) has been proposed, characterized, and a comparative analysis with the Conventional Charge Plasma-based Nanowire Transistor (CCPNWT) and the Stack-Gate-Oxide CPNWT (SGO-CPNWT) has been investigated. The effects of stacking a high-κ gate oxide with a low-κ gate oxide beneath the gate and segmenting the gate oxide with a high-κ oxide at the source side and low-κ oxide at the drain side have been analyzed with the short channel effects (SCEs) parameters and radio-frequency (RF) / analog figure of merits have been analyzed. The HGO-CPNWT demonstrates enhanced performances in terms of Ion/Ioff of 1.66×108, subthreshold slope (SS) of 65.74 mV/decade, drain induced barrier lowering (DIBL) of 47.857 mV/V, peak transconductance (gm) of 3.43×10-5 S/μm, and peak cut-off frequency (ft) of 114 GHz. The simulation employs a comprehensive quantum transport model (NEGF), and the comparative impacts of adjusting channel length (Lg), nanowire radius (r), and gate oxide thickness (Tox) are studied.

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Section: Device Structure and Methodologymentioning

confidence: 99%

Section: Analog/rf Performancementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Comparative analysis of gate-oxide engineering in charge plasma based nanowire transistor

Debnath,

Sikder,

Singha

2023

Eng. Res. Express

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“…The core consists of silicon dioxide (SiO 2 ) with a platinum electrode whose work function is equal to 5.93 eV and a hafnium electrode whose work function is 3.9 eV to form the source and drain, respectively, because the device is dopingless [16]. Application of the charge plasma technique allows the elimination of the doping techniques implemented at high temperatures [17]. The core is further covered with a layer of intrinsic silicon with a concentration of 10 15 atoms/cm 3 over which another layer of SiO 2 , gate oxide is wrapped.…”

Section: Device Structuresmentioning

confidence: 99%

Design and investigation of negative capacitance–based core‐shell dopingless nanotube tunnel field‐effect transistor

Apoorva

Kumar

Amin

et al. 2021

IET Circuits, Devices & Systems

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Investigation and analysis of a ferroelectric material-based dopingless nanotube tunnel field-effect transistor are conducted using a lead zirconate titanate (PZT) gate stack to induce negative capacitance in the device. Landau-Khalatnikov equations are used in deriving the parameter values of the ferroelectric material to ensure accurate results. The nanotube structure of the tunnel field-effect transistor allows for better electrostatic control owing to its gate-all-around structure. Incorporation of negative capacitance further reduces the voltage supply requirement and power consumption of the structure while simultaneously improving switching. In addition, the device is studied for varying thicknesses of the dielectric PZT material. The threshold voltage of the device under study was calculated as 0.281 V, and the average subthreshold slope of the device was reduced to 18.271 mV/decade, far below the thermionic limit of 60 mV/decade. This is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited.

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“…VGS controls the amount of inversion charge that carries the current. VDS controls the electric field that drifts the inversion charge from the source to drain [6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22]. By expanding on these principles, the model of the Inversion-Layer Centroid for the 3D FinFET taking into consideration Quantum effects can be developed.…”

Section: Equations Used For 3d Finfetmentioning

confidence: 99%

Indium Gallium Zinc Oxide FinFET Compared with Silicon FinFET

Matebesi

Ditshego

2021

JNanoR

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Indium gallium zinc oxide fin-field effect transistor (IGZO FinFET) characteristics are investigated and then compared with Zinc oxide fin-field effect transistor (ZnO FinFET) and the Silicon fin-field effect transistor (Si FinFET). This was done using 3D simulation. The threshold voltage for Si, ZnO, and IGZO is 0.75 V, 0.30 V and 0.05 V respectively. The silicon device has the highest transconductance (5.0 x 10-7 S) and performs better than the other devices because it has less fixed charge defects. IGZO has the second-best value of Gm (3.6 x 10-7 S), ZnO has the least value of Gm (3.4 x 10-7 S). Si device has the least drain current (IDS) value of 2.0 x 10-7 A, ZnO device has a better IDS value of 6.2 x 10-6 A while IGZO device has the best IDS value of 1.6 x 10-5 A. IGZO is better than Si by two (2) order magnitude. The field effect mobility is 50.0 cm2/Vs for all three devices.

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Charge plasma technique based dopingless accumulation mode junctionless cylindrical surrounding gate MOSFET: analog performance improvement

Cited by 20 publications

References 20 publications

Comparative analysis of gate-oxide engineering in charge plasma based nanowire transistor

Comparative analysis of gate-oxide engineering in charge plasma based nanowire transistor

Design and investigation of negative capacitance–based core‐shell dopingless nanotube tunnel field‐effect transistor

Indium Gallium Zinc Oxide FinFET Compared with Silicon FinFET

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