Charge-Domain Signal Processing of Direct RF Sampling Mixer with Discrete-Time Filters in Bluetooth and GSM Receivers

Ho, Yo-Chuol; Staszewski, Robert Bogdan; Muhammad, K.; Hung, Chih‐Ming; Leipold, Dirk; Maggio, K.

doi:10.1155/wcn/2006/62905

Cited by 26 publications

(17 citation statements)

References 4 publications

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“…It consists of an LNTA, a pair of quadrature mixers, and DT sampling LPFs. The received RF signal is amplified and converted into current, i RF , by the LNTA with high output impedance [22]. This current is then downconverted to ZIF by the quadrature mixers.…”

Section: Discrete-time Receivermentioning

confidence: 99%

A Fully Integrated Discrete-Time Superheterodyne Receiver

Tohidian

Madadi

Staszewski

2017

IEEE Trans. VLSI Syst.

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The zero/low intermediate frequency (IF) receiver (RX) architecture has enabled full CMOS integration. As the technology scales and wireless standards become ever more challenging, the issues related to time-varying dc offsets, the second-order nonlinearity, and flicker noise become more critical. In this paper, we propose a new architecture of a superheterodyne RX that attempts to avoid such issues. By exploiting discrete-time (DT) operation and using only switches, capacitors, and inverter-based gm-stages as building blocks, the architecture becomes amenable to further scaling. Full integration is achieved by employing a cascade of four complex-valued passive switched-cap-based bandpass filters sampled at 4× of the local oscillator rate that perform IF image rejection. Channel selection is achieved through an equivalent of the seventh-order filtering. A new twofold noise-canceling low-noise transconductance amplifier is proposed. Frequency domain analysis of the RX is presented by the proposed DT model. The RX is wideband and covers 0.4-2.9 GHz with a noise figure of 2.9-4 dB. It is implemented in 65-nm CMOS and consumes 48-79 mW.

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Section: Discrete-time Receivermentioning

confidence: 99%

A Fully Integrated Discrete-Time Superheterodyne Receiver

Tohidian

Madadi

Staszewski

2017

IEEE Trans. VLSI Syst.

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“…It is analyzed in detail in [6]. This concept is transferred from a serial to a parallel concept in [7].…”

Section: Sample Mixermentioning

confidence: 99%

A double-mixing sampling receiver concept to enable GNSS-L1/L5 double-band reception

Schultz

Duerdodt

Hammes

et al. 2012

International Multi-Conference on Systems, Sygnals &Amp; Devices

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A double mixing architecture is presented which enables a simultaneous two-band reception of global navigation satellite system (GNSS) signals. State of the art of sampling receivers is discussed together with its main drawbacks in a simultaneous double-band reception. A circuit with low implementation effort is proposed to relax the filter requirements in the signal path. The concept is applied in a global navigation satellite system context, where receiving two bands can significantly improve performance. Simulation results on the proposed system demonstrate feasibility. This concept enhances the robustness versus blocking signals in the GNSS example by up to 37 dB at fs/2.

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“…In both of these systems, after conversion of the RF signal to baseband and blocker suppression, a set of low-pass filtering processes is required to achieve a good stop-band rejection, avoiding the aliasing after A/D conversion. Moreover, low-pass filters (LPFs) play a key role in many applications, such as wireless communications, [3][4][5][6][7][8][9] hard-disk drives, 10,11 audio and video signal processing, 12 reconstructing filtering in a DAC, 13 and prefiltering in a sampling system to prevent aliasing. One of the most important concerns of such systems is noise.…”

Section: Introductionmentioning

confidence: 99%

A mathematical method to realize complex poles in a high‐order passive switched‐capacitor filter

Niaboli-Guilani

Ardeshir

2019

Circuit Theory & Apps

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Summary A high‐order discrete‐time IIR low‐pass with complex poles using charge sampling is presented in a single‐stage structure by using a mathematical strategy. In comparison with the analog complex‐poles Gm‐C filters, the proposed filter consumes lower power and has good linearity, and all of the tunings are implemented only by capacitor sizes. The proposed filter is a seventh‐order Butterworth, but this method can be generalized to implement other complex pole filters like Tchebyshev and Elliptic. Post‐layout simulation results in 130‐nm complementary metal‐oxide‐semiconductor (CMOS) show an IIP3 of +18 dBm and a noise figure of 5 dB. The filter has a rejection of more than 110 dB in its stop band and consumes 1.5 mW with a 1.6‐V supply voltage, and circuit occupies an about 0.12 mm2 of silicon.

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Charge-Domain Signal Processing of Direct RF Sampling Mixer with Discrete-Time Filters in Bluetooth and GSM Receivers

Cited by 26 publications

References 4 publications

A Fully Integrated Discrete-Time Superheterodyne Receiver

A Fully Integrated Discrete-Time Superheterodyne Receiver

A double-mixing sampling receiver concept to enable GNSS-L1/L5 double-band reception

A mathematical method to realize complex poles in a high‐order passive switched‐capacitor filter

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