Charge Collection in Power MOSFETs for SEB Characterisation—Evidence of Energy Effects

Ferlet-Cavrois, V.; Sturesson, Fredrik; Zadeh, Ali; Santin, G.; Truscott, P.R.; Poivey, C.; Schwank, J.R.; Peyre, D.; Binois, C.; Beutier, T.; Luu, A.; Poizat, Marc; Chaumont, G.; Harboe-Sørensen, R.; Bezerra, F.; Ecoffet, R.

doi:10.1109/tns.2010.2086077

Cited by 20 publications

(8 citation statements)

References 37 publications

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“…The generation rate of the created charges is described by spatial and temporal Gaussian functions. Considering that the linear energy transfer (LET) is unchanged in a certain range, we choose LET which is constant along the ionizing track so as to facilitate the study and the result interpretation [14], [30]. The hypothetical ion fully penetrates the device.…”

Section: Seb Hardened Structure Designmentioning

confidence: 99%

Single-Event Burnout Hardened Structure of Power UMOSFETs With Schottky Source

Wang

Zhang

Cao

et al. 2014

IEEE Trans. Power Electron.

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This paper investigates the single-event burnout (SEB) simulation results for both the standard and hardened structure of power U-shape gate MOSFETs (UMOSFETs). The Schottky source is proposed to reduce the work of the parasitic bipolar transistor inherent to the device. The hardened structure of power UMOSFETs with the Schottky source and N buffer layer is given, which can work normally and improve the SEB performance effectively. Both 70-and 120-V power MOSFETs are simulated and discussed in this paper. The SEB threshold voltages are increased to more than 94 percent of the breakdown voltages for both 70-and 120-V hardened structure, compared to 54 percent for standard power UMOSFETs.Index Terms-Hardened structure, power UMOSFET, Schottky source, single-event burnout (SEB).

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Section: Seb Hardened Structure Designmentioning

confidence: 99%

Single-Event Burnout Hardened Structure of Power UMOSFETs With Schottky Source

Wang

Zhang

Cao

et al. 2014

IEEE Trans. Power Electron.

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show abstract

“…This "diodelike" bias configuration is used to collect most of the charge generated in the epitaxial layer while avoiding charge amplification or burnout events. It was indeed shown in [17] that for this particular transistor and at this voltage, there is an "almost perfect equality between the collected charge and the deposited charge", for half of the measured events. For this type of device, the statistical distribution of collected charge indeed exhibits two peaks, which can be related to strikes in the gate and in the source respectively [17].…”

Section: A Devices Under Testmentioning

confidence: 65%

“…It was indeed shown in [17] that for this particular transistor and at this voltage, there is an "almost perfect equality between the collected charge and the deposited charge", for half of the measured events. For this type of device, the statistical distribution of collected charge indeed exhibits two peaks, which can be related to strikes in the gate and in the source respectively [17]. In the following, only one peak is considered for the analysis, the one for which the collected charge can be related to the generated charge.…”

Section: A Devices Under Testmentioning

confidence: 65%

“…They are the MM2G devices fabricated by STMicroelectronics described in [17]. In that case, the highly doped drain region is topped by a 17 thick low-doped epitaxial layer, which is considered as the sensitive volume.…”

Section: A Devices Under Testmentioning

confidence: 99%

“…In the following, only one peak is considered for the analysis, the one for which the collected charge can be related to the generated charge. This is the one corresponding to ion hits in the gate area [17], where the silicon thickness is the least impacted by process induced variations. The legitimacy of comparing transistors with diodes data will be discussed in details in the following.…”

Section: A Devices Under Testmentioning

confidence: 99%

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