Charge Collection Efficiency Related to Damage in MOS Capaciors

Xapsos, M.A.; Campbell, A.B.; Knudson, A.R.; Stapor, W.J.; Shapiro, P.; Palmer, T.; McDonald, P.T.; Swickert, S.L.

doi:10.1109/tns.1987.4337455

Cited by 18 publications

(10 citation statements)

References 7 publications

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“…For n-substrate capacitors, the total collected charge increases as the bias is made more negative and saturates at high negative bias levels. A qualitatively similar bias dependence was previously observed by Xapsos et al for n-substrate thermal oxide capacitors [5] and by Musseau et al [6] for SOI buried oxide capacitors.…”

Section: A Experimental Results-focused Microbeamsupporting

confidence: 88%

“…However, this conductive pipe model was not verified either experimentally or through simulations, and as pointed out by Campbell et al [4], it seems unlikely that such a conductive path would remain in existence long enough to produce significant charge transfer. Another possible mechanism for charge collection in areas other than the gate could be associated with displacement currents (capacitive discharge) [5]- [7]. Displacement currents across the buried oxide can be induced as charge is generated in the SOI substrate by an ion strike, perturbing the electric fields in the substrate near the oxide/substrate interface.…”

Section: Introductionmentioning

confidence: 99%

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Charge collection in SOI capacitors and circuits and its effect on SEU hardness

Schwank

Dodd

Shaneyfelt

et al. 2002

IEEE Trans. Nucl. Sci.

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Focused ion microbeam and broadbeam heavy-ion experiments on capacitors and SRAMs are used to investigate increased saturation upset cross sections recently observed in some silicon-on-insulator (SOI) integrated circuits (ICs). Experiments performed on capacitors show a very strong bias and oxide thickness dependence for charge collection. In combination with three-dimensional (3-D) simulations, these data suggest that the mechanism for charge collection in capacitors is due to perturbation of the substrate electric fields by charge deposition in the substrate. For substrates biased in depletion, these perturbations induce displacement currents through the oxide. Charge collection by displacement currents can be substantially reduced or mitigated by using heavily doped substrates. Experiments performed on SRAMs also show enhanced charge collection from displacement currents. However, experimental data and 3-D simulations show that for SRAMs, a second mechanism also contributes to charge collection. The 3-D simulations suggest that the charge collection results from drain and body-tie heavy-ion strikes within a few tenths of a micron of the body-to-drain junctions. These charge collection mechanisms can substantially reduce the SEU hardness and soft-error reliability of commercial SOI ICs.

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Section: A Experimental Results-focused Microbeamsupporting

confidence: 88%

Section: Introductionmentioning

confidence: 99%

Charge collection in SOI capacitors and circuits and its effect on SEU hardness

Schwank

Dodd

Shaneyfelt

et al. 2002

IEEE Trans. Nucl. Sci.

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show abstract

“…More recently, Musseau et al performed charge collection experiments on source/buried oxide (BOX)/substrate capacitors as a function of substrate bias [28]. The measured charge collection was ascribed to "substrate funneling," in which the ion track perturbs the electric field under the capacitor when biased in inversion and causes a capacitive discharge [10], [29]. It was predicted that substrate funneling would probably not degrade the sensitivity of SOI technologies.…”

Section: A Charge Collection Mechanisms In Soimentioning

confidence: 99%

SEU-sensitive volumes in bulk and SOI SRAMs from first-principles calculations and experiments

Dodd

Shaneyfelt

Horn

et al. 2001

IEEE Trans. Nucl. Sci.

176

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Large-scale three-dimensional (3-D) device simulations, focused ion microscopy, and broadbeam heavy-ion experiments are used to determine and compare the SEU-sensitive volumes of bulk-Si and SOI CMOS SRAMs. Single-event upset maps and cross-section curves calculated directly from 3-D simulations show excellent agreement with broadbeam cross section curves and microbeam charge collection and upset images for 16 K bulk-Si SRAMs. Charge-collection and single-event upset (SEU) experiments on 64 K and 1 M SOI SRAMs indicate that drain strikes can cause single-event upsets in SOI ICs. 3-D simulations do not predict this result, which appears to be due to anomalous charge collection from the substrate through the buried oxide. This substrate charge-collection mechanism can considerably increase the SEU-sensitive volume of SOI SRAMs, and must be included in single-event models if they are to provide accurate predictions of SOI device response in radiation environments.

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“…The two set of capacitors were irradiated with a positive gate bias (VG=+15 V) to induce a significant charge collection. Thus, the applied gate bias must form a depletion region in the silicon substrate [10].…”

Section: Introductionmentioning

confidence: 99%

“…However, due to holes diffusion coefficient to electrons diffusion coefficient ratio being one-third (assumption done in the simulation code synopsis) a positive charge appears in the substrate. This phenomenon is well known and described as ambipolar diffusion process [10]. pm)..…”

Section: Introductionmentioning

confidence: 99%