Characterizing SRAM and FF soft error rates with measurement and simulation

Hashimoto, Masanori; Kobayashi, Kazutoshi; Furuta, Jun; Abe, Shingo; Watanabe, Yukinobu

doi:10.1016/j.vlsi.2019.03.005

Cited by 13 publications

(14 citation statements)

References 60 publications

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“…31 (4): 1921-1936(2023 Norhuzaimin Julai, Farhana Mohamad, Rohana Sapawi and Shamsiah Suhaili of process nodes in contemporary CMOS technology (Hubert et al, 2015). The generation of soft error effects can be categorised into three phases, namely, the charge injected through particle collision in the active circuit location, the transmission of the injected charge into the system, and the collection of the charge into the vulnerable area of the device (Autran & Munteanu, 2015;Hashimoto et al, 2019).…”

Section: Introductionmentioning

confidence: 99%

Probability Formulation of Soft Error in Memory Circuit

Julai¹,

Mohamad²,

Sapawi³

et al. 2023

JST

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Downscaling threatens the designers invested in integrity and error mitigation against soft errors. This study formulated the probability of soft error changing the logic state of a Differential Logic with an Inverter Latch (DIL). Using Cadence Virtuoso, current pulses were injected into various nodes in stages until a logic flip was instigated. The voltage and temperature parameters were increased to observe the current level changes over time. The critical charge from each stage was obtained, and a method to formulate the probability of each instance was developed. The voltage produced a higher effect of the change to the critical charge of any instance as compared to temperature. The findings revealed that the N-channel metal-oxide semiconductor (NMOS) drain is more vulnerable to temperature and voltage variation than P-channel metal-oxide semiconductor (PMOS).

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Section: Introductionmentioning

confidence: 99%

Probability Formulation of Soft Error in Memory Circuit

Julai¹,

Mohamad²,

Sapawi³

et al. 2023

JST

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“…However, with these advanced nano-scale CMOS technologies, the amount of critical charge stored on a node in a circuit decreases due to the decreasing supply voltages and node capacitances. As a result, advanced CMOS circuits and systems are becoming more and more prone to soft errors induced by the striking of particles, such as protons, heavy particles, electrons, muons, and alpha particles [2]. Soft errors may cause the logic value stored inside SRAM cells to be flipped, thus possibly causing serious system failure.…”

Section: Introductionmentioning

confidence: 99%

Quadruple and Sextuple Cross-Coupled SRAM Cell Designs With Optimized Overhead for Reliable Applications

Yan

Xiang

Cao

et al. 2022

IEEE Trans. Device Mater. Relib.

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“…As a result, the values of circuit nodes can be easily disturbed by radiation effects. The striking of radiative high-energy particles, such as neutrons, alpha particles, protons, heavy ions, electrons, and muons as well as the irradiation of high-energy X-ray and laser, etc., can easily cause soft errors to modern advanced CMOS circuits [1][2]. Soft errors can cause potential data corruptions, execution errors, and even system crashes.…”

Section: Introductionmentioning

confidence: 99%

Dual-Interlocked-Storage-Cell-Based Double-Node-Upset Self-Recoverable Flip-Flop Design for Safety-Critical Applications

Yan

Cui

et al. 2020

2020 IEEE International Symposium on Circuits and Systems (ISCAS)

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This paper presents a novel dual-interlocked storagecell (DICE)-based double-node-upset (DNU) self-recoverable, namely DURI-FF, in the nano-scale CMOS technology. The master latch of the DURI-FF cell consists of three transmission gates (TGs) and three interlocked DICEs with three common nodes. The common nodes are connected to TGs for value initialization. The slave latch of the DURI-FF cell comprises six TGs, six inverters and three interlocked DICEs. The outputs of the inverters respectively feed the internal nodes of the slave latch. The interlocked DICEs make the master latch and the slave latch DNU self-recoverable. Simulation results validate the DNU self-recoverability of the proposed DURI-FF cell. Moreover, compared with the state-of-the-art hardened flip-flop cells, the proposed DURI-FF cell achieves roughly 43% delay reduction at the cost of moderate silicon area and power dissipation.

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Characterizing SRAM and FF soft error rates with measurement and simulation

Cited by 13 publications

References 60 publications

Probability Formulation of Soft Error in Memory Circuit

Probability Formulation of Soft Error in Memory Circuit

Quadruple and Sextuple Cross-Coupled SRAM Cell Designs With Optimized Overhead for Reliable Applications

Dual-Interlocked-Storage-Cell-Based Double-Node-Upset Self-Recoverable Flip-Flop Design for Safety-Critical Applications

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