Proceedings of the 2016 ACM SIGPLAN International Symposium on Memory Management 2016
DOI: 10.1145/2926697.2926702
|View full text |Cite
|
Sign up to set email alerts
|

Characterizing emerging heterogeneous memory

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
3
1
1

Citation Types

0
11
0

Year Published

2016
2016
2021
2021

Publication Types

Select...
6
1

Relationship

0
7

Authors

Journals

citations
Cited by 17 publications
(11 citation statements)
references
References 28 publications
0
11
0
Order By: Relevance
“…Du et. al [19] develop a PIN-based o ine pro ling tool to collect memory traces and provide guidance for placing data on HMS.…”
Section: Related Workmentioning
confidence: 99%
See 2 more Smart Citations
“…Du et. al [19] develop a PIN-based o ine pro ling tool to collect memory traces and provide guidance for placing data on HMS.…”
Section: Related Workmentioning
confidence: 99%
“…Our initial performance evaluation with HPC workloads (Section 2) shows that there is 1.09x-8.4x slowdown on NVM-based systems, depending on bandwidth and latency features of NVM. Because of the limitation of NVM, NVM is o en paired with a small fraction of DRAM to form a heterogeneous memory system (HMS) [8,10,13,19,24,26]. By selectively placing frequently accessed data in the small amount of DRAM available in HMS, we are able to exploit the cost and scaling bene ts of NVM while minimizing the limitation of NVM with DRAM.…”
Section: Introductionmentioning
confidence: 99%
See 1 more Smart Citation
“…Current state-of-the-art approaches rely on detailed a priori application profiles to establish the relative priority of all of the application data structures [12,28,33]. However, such approaches have limited applicability for complex applications, applications exhibiting data-dependent variability in their execution, or requiring crossapplication-component data exchanges.…”
Section: Design Componentsmentioning
confidence: 99%
“…Our initial performance evaluation with HPC workloads (Section 2) shows that there is 1.09x-8.4x slowdown on NVM-based systems, depending on bandwidth and latency features of NVM. Because of the limitation of NVM, NVM is often paired with a small fraction of DRAM to form a heterogeneous memory system (HMS) [1][2][3][4][5][6][7] . By selectively placing frequently-accessed data in the small amount of DRAM available in HMS, we are able to exploit the cost and scaling benefits of NVM while minimizing the limitation of NVM with DRAM.…”
Section: Introductionmentioning
confidence: 99%