Unimem: Runtime Data Management on Non-Volatile Memory-Based Heterogeneous Main Memory for High Performance Computing

Wu, Kai; Li, Dong

doi:10.1007/s11390-020-0942-z

Cited by 18 publications

(37 citation statements)

References 27 publications

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“…Dynamic data placement has been employed to enable high performance on heterogeneous memory [2,12,22,24,46,57,58,61,76,78,79,82,86,87]. Most of those solutions are application agnostic, which means that they track page (or data) access frequency [2,12,22,24,78,79,82,87] or manage DRAM as a hardware cache for PMM [46,57,76,86] without the knowledge of data semantics. However, the data semantics gives critical indications on memory access patterns, which is useful to direct data placement and avoid unnecessary data movement.…”

Section: Dynamic Data Placement Based On Data Semanticsmentioning

confidence: 99%

“…All experiments were conducted on a single socket with one thread per physical core. Similar to recent work [24,44,78,80], we use one-socket evaluation to highlight data movement between DRAM and PMM. Each workload is run 10 times and we report the average execution time.…”

Section: Evaluation 51 Evaluation Setupmentioning

confidence: 99%

“…RAMinate [22], Heteros [24], Yan et al [82] propose the state-of-the-art memory management solutions for general purpose which guides page placement based on an existing Linux page replacement mechanism. Application-specific HM management solutions [8,11,13,18,33,35,45,47,75,78,79,85] leverage domain knowledge to further improve performance. MyNVM [13] proposes a software-managed multi-level caches policy to treat DRAM and NVM as caches for hard drives.…”

Section: Related Workmentioning

confidence: 99%

“…Effectively placing data objects of an SpTCSeq in DRAM and PMM for high performance is critical to use PMM to address the memory capacity problem faced by SpTCSeq. To decide data placement on HM, the traditional solutions track page (or data) access frequency [2,12,22,24,58,61,78,79,82,87] or manage DRAM as a hardware cache for PMM [46,57,76,86], and then reactively place frequently accessed data objects into DRAM subject to the DRAM capacity constraint. However, those solutions are application-agnostic, and cause unnecessary and frequent data movement because of short-term variance in memory access patterns.…”

Section: Introductionmentioning

confidence: 99%

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Athena

Liu

Gioiosa

et al. 2021

Proceedings of the ACM International Conference on Supercomputing

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Sparse tensor contraction sequence has been widely employed in many fields, such as chemistry and physics. However, how to efficiently implement the sequence faces multiple challenges, such as redundant computations and memory operations, massive memory consumption, and inefficient utilization of hardware. To address the above challenges, we introduce Athena, a high-performance framework for SpTC sequences. Athena introduces new data structures, leverages emerging Optane-based heterogeneous memory (HM) architecture, and adopts stage parallelism. In particular, Athena introduces shared hash table-represented sparse accumulator to eliminate unnecessary input processing and data migration; Athena uses a novel data-semantic guided dynamic migration solution to make the best use of the Optane-based HM for high performance; Athena also co-runs execution phases with different characteristics to enable high hardware utilization. Evaluating with 12 datasets, we show that Athena brings 327-7362× speedup over the state-ofthe-art SpTC algorithm. With the dynamic data placement guided by data semantics, Athena brings performance improvement on Optane-based HM over a state-of-the-art software-based data management solution, a hardware-based data management solution, and PMM-only by 1.58×, 1.82×, and 2.34× respectively. Athena also showcases its effectiveness in quantum chemistry and physics scenarios. CCS CONCEPTS• Mathematics of computing → Mathematical software performance; • Computing methodologies → Shared memory algorithms.

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Section: Dynamic Data Placement Based On Data Semanticsmentioning

confidence: 99%

Section: Evaluation 51 Evaluation Setupmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Athena

Liu

Gioiosa

et al. 2021

Proceedings of the ACM International Conference on Supercomputing

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“…As a result, PM and DRAM form a heterogeneous memory (HM) system. How to place and migrate data between PM and DRAM to enjoy the speed of DRAM and capacity of PM remains active research [7,11,22,26,39,40].…”

Section: Introductionmentioning

confidence: 99%

Optimizing large-scale plasma simulations on persistent memory-based heterogeneous memory with effective data placement across memory hierarchy

Ren

Luo

et al. 2021

Proceedings of the ACM International Conference on Supercomputing

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Particle simulations of plasma are important for understanding plasma dynamics in space weather and fusion devices. However, production simulations that use billions and even trillions of computational particles require high memory capacity. In this work, we explore the latest persistent memory (PM) hardware to enable large-scale plasma simulations at unprecedented scales on a single machine. We use WarpX, an advanced plasma simulation code which is mission-critical and targets future exascale systems. We analyze the performance of WarpX on PM-based heterogeneous memory systems and propose to make the best use of memory hierarchy to avoid the impact of inferior performance of PM. We introduce a combination of static and dynamic data placement, and processor-cache prefetch mechanism for performance optimization. We develop a performance model to enable efficient data migration between PM and DRAM in the background, without reducing available bandwidth and parallelism to the application threads. We also build an analytical model to decide when to prefetch for the best use of caches. Our design achieves 66.4% performance improvement over the PM-only baseline and outperforms DRAM-cached, NUMA first-touch, and a state-of-the-art software solution by 38.8%, 45.1% and 83.3%, respectively. CCS CONCEPTS• Software and its engineering → Software performance.

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Footprint-Aware Power Capping for Hybrid Memory Based Systems

Arima

Hanawa

Trinitis

et al. 2020

Lecture Notes in Computer Science

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High Performance Computing (HPC) systems are facing severe limitations in both power and memory bandwidth/capacity. By now, these limitations have been addressed individually: to improve performance under a strict power constraint, power capping, which sets power limits to components/nodes/jobs, is an indispensable feature; and for memory bandwidth/capacity increase, the industry has begun to support hybrid main memory designs that comprise multiple different technologies including emerging memories (e.g., 3D stacked DRAM or Non-Volatile RAM) in one compute node. However, few works look at the combination of both trends. This paper explicitly targets power managements on hybrid memory based HPC systems and is based on the following observation: in spite of the system software's efforts to optimize data allocations on such a system, the effective memory bandwidth can decrease considerably when we scale the problem size of applications. As a result, the performance bottleneck component changes in accordance with the footprint (or data) size, which then also changes the optimal power cap settings in a node. Motivated by this observation, we propose a power management concept called footprint-aware power capping (FPCAP) and a profile-driven software framework to realize it. Our experimental result on a real system using HPC benchmarks shows that our approach is successful in correctly setting power caps depending on the footprint size while keeping around 93/96% of performance/power-efficiency compared to the best settings.

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Unimem: Runtime Data Management on Non-Volatile Memory-Based Heterogeneous Main Memory for High Performance Computing

Cited by 18 publications

References 27 publications

Athena

Athena

Optimizing large-scale plasma simulations on persistent memory-based heterogeneous memory with effective data placement across memory hierarchy

Footprint-Aware Power Capping for Hybrid Memory Based Systems

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