Characterization of TCC on chip-multiprocessors

McDonald, Austen; Chung, JaeWoong; Chafi, Hassan; Minh, Chi Cao; Carlstrom, Brian D.; Hammond, Lance; Kozyrakis, Christos; Olukotun, Kunle

doi:10.1109/pact.2005.11

Cited by 50 publications

(45 citation statements)

References 36 publications

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“…Transactional memory systems generally fall into two categories: those that are hardware-based [8], [9], and those that are software-based [4], [10]- [12]. Hardware-based systems are presently in the conceptual stage, and can only be studied through simulation.…”

Section: A Choosing a Tm Systemmentioning

confidence: 99%

Parallelizing FPGA placement using Transactional Memory

Birk

Steffan

Anderson

2010

2010 International Conference on Field-Programmable Technology

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Abstract-To capitalize on the growing abundance of multicore hardware, FPGA vendors have begun to parallelize the most compute intensive algorithms in their CAD software. However, parallelization is a painstaking and hence expensive process that limits the number of algorithms that can be cost-effectively parallelized. Transactional Memory (TM) promises an easier-touse alternative to locks for critical sections in threaded codeallowing programmers to avoid deadlocks and data races, and also allowing critical sections to execute in parallel as long as they dynamically access independent data. In this paper, we present our work on using TM to parallelize simulated annealingbased placement for FPGAs. In particular, we use a software TM (TinySTM) to parallelize the placement phase of Versatile Place and Route (VPR) 5.0.2 [1]. With TM we very quickly produced a parallel and correct version of the software, allowing us to focus on incrementally tuning performance. We describe our experiences in tuning the TM system and CAD software, and the interesting algorithmic trade-offs that exist. In the end, we found that optimized transactional placement has the potential for scalable performance: our non-deterministic implementation achieves self-relative speedups over a single thread of 1.82x, 3.62x and 7.27x at 2, 4, and 8 threads respectively with little quality degradation. However, hardware support for TM is likely required to overcome the overheads of STM, as our implementation's single thread performance is 8x slower than sequential VPR.

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Section: A Choosing a Tm Systemmentioning

confidence: 99%

Parallelizing FPGA placement using Transactional Memory

Birk

Steffan

Anderson

2010

2010 International Conference on Field-Programmable Technology

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“…Transactional Coherence and Consistency (TCC) [41,39,40,67,16] is based on the observation that for well synchronized programs, coherence and consistency are only needed to be maintained at synchronization points. TCC is proposed as a new shared memory model where atomic transactions always are the basic units of work and communication, as well as for memory coherence and consistency.…”

Section: Transactional Coherence and Consistency Tccmentioning

confidence: 99%

Transactional memory

Grahn¹

2010

Journal of Parallel and Distributed Computing

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Current and future processor generations are based on multicore architectures where the performance increase comes from an increasing number of cores on a chip. In order to utilize the performance potential of multicore architectures the programs also need to be parallel, but writing parallel programs is a non-trivial task. Transactional memory tries to ease parallel program development by providing atomic and isolated execution of code sequences, enabling software composability and protected access to shared data. In addition, transactional memory has the ability to execute atomic code sequences in parallel as long as no data conflicts occur. Transactional memory implementation proposals exist for both hardware and software, as well as hybrid solutions. This special issue on transactional memory introduces transactional memory as a concept, presents an overview of some of the most important approaches so far, and finally, includes five articles that advances the state-of-the-art in transactional memory research.

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“…The Atomos language [4] is a Java extension that supports transactions through atomic blocks and also the retry construct to block transactions. Transactions are supported by the Transactional Coherence and Consistency hardware transactional memory model (TCC) [18], and programs are run on a simulator that implements the (TCC) architecture. No support composing transactions as alternatives is given.…”

Section: Related Workmentioning

confidence: 99%

A Domain Specific Language for Composable Memory Transactions in Java

Bois

Echevarria

2009

Domain-Specific Languages

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Abstract. In this paper we present CMTJava, a domain specific language for composable memory transactions [7] in Java. CMTJava provides the abstraction of transactional objects. Transactional objects have their fields accessed only by special get and set methods that are automatically generated by the compiler. These methods return transactional actions as a result. A transactional action is an action that, when executed, will produce the desired effect. Transactional actions can only be executed by the atomic method. Transactional actions are first class values in Java and they are composable: transactions can be combined to generate new transactions. The Java type system guarantees that the fields of transactional objects will never be accessed outside a transaction. CMTJava supports the retry and orElse constructs from STM Haskell. To validate our design we implemented a simple transactional system following the description of the original Haskell system. CMTJava is implemented as a state passing monad using BBGA closures, a Java extension that supports closures in Java.

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Characterization of TCC on chip-multiprocessors

Abstract: Abstract

Cited by 50 publications

References 36 publications

Parallelizing FPGA placement using Transactional Memory

Parallelizing FPGA placement using Transactional Memory

Transactional memory

A Domain Specific Language for Composable Memory Transactions in Java

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