Characterization of silicon heterojunctions for solar cells

Kleider, Jean‐Paul; Alvarez, José; Ankudinov, A. V.; Gudovskikh, A. S.; Гущина, Е. В.; Labrune, M.; Maslova, Olga; Favre, Wilfried; Gueunier‐Farret, Marie‐Estelle; Cabarrocas, Pere Roca i; Terukov, E. I.

doi:10.1186/1556-276x-6-152

Cited by 20 publications

(18 citation statements)

References 12 publications

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“…14,15 Until now, the inversion layer has been considered only as a tool to characterize the band offsets at the a-Si:H/c-Si interface 16,17 and its influence on lateral transport in operating devices has not yet been analyzed. Lateral transport through an inversion layer is successfully leveraged in modulationdoped field-effect transistors 18 and in metal-insulatorconductor inversion layer solar cells.…”

Section: Introductionmentioning

confidence: 99%

Analysis of lateral transport through the inversion layer in amorphous silicon/crystalline silicon heterojunction solar cells

Filipič

Holman

Smole

et al. 2013

Journal of Applied Physics

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In amorphous/crystalline silicon heterojunction solar cells, an inversion layer is present at the front interface. By combining numerical simulations and experiments, we examine the contribution of the inversion layer to lateral transport and assess whether this layer can be exploited to replace the front transparent conductive oxide (TCO) in devices. For this, heterojunction solar cells of different areas (2 Â 2, 4 Â 4, and 6 Â 6 mm 2 ) with and without TCO layers on the front side were prepared. Laser-beam-induced current measurements are compared with simulation results from the ASPIN2 semiconductor simulator. Current collection is constant across millimeter distances for cells with TCO; however, carriers traveling more than a few hundred microns in cells without TCO recombine before they can be collected. Simulations show that increasing the valence band offset increases the concentration of holes under the surface of n-type crystalline silicon, which increases the conductivity of the inversion layer. Unfortunately, this also impedes transport across the barrier to the emitter. We conclude that the lateral conductivity of the inversion layer may not suffice to fully replace the front TCO in heterojunction devices. V C 2013 AIP Publishing LLC.

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Section: Introductionmentioning

confidence: 99%

Analysis of lateral transport through the inversion layer in amorphous silicon/crystalline silicon heterojunction solar cells

Filipič

Holman

Smole

et al. 2013

Journal of Applied Physics

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“…The double heterojunction structures (p)a‐Si:H/(n)c‐Si/(n)a‐Si:H were simulated with typical values for the c‐Si and a‐Si:H material parameters, whereas the thicknesses and doping level corresponded to the experimental samples. The values of conduction and valence band offsets were set equal to 0.15 and 0.45 eV, respectively . For the reference sample, a low bulk defect density (5 × 10 9 cm −3 ) was introduced in c‐Si, which corresponds to a high lifetime value in bulk silicon (2 ms).…”

Section: Resultsmentioning

confidence: 99%

Effect of Cryogenic Dry Etching on Minority Charge Carrier Lifetime in Silicon

Kudryashov

Gudovskikh

Baranov

et al. 2019

Physica Status Solidi (a)

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Micro‐ and nanostructured silicon surface application is a promising way of photovoltaic development. An enhancement of optical absorption in solar cells can be achieved, for example, using vertically aligned silicon nanostructures with high aspect ratios. Cryogenic plasma etching is a suitable method for such structures' formation; however, there is still lack of data describing an effect of cryogenic inductively coupled plasma (ICP) etching on defect formation in silicon (Si). The defects may act as recombination centers, leading to solar cell characteristics degradation. Herein, the cryogenic dry etching effects on defect formation in float‐zone (FZ) n‐type silicon substrates and on the photovoltaic properties of solar cells made of plasma‐etched silicon substrate are presented. The decrease in low‐injection minority carrier lifetime in silicon from 0.85 to 0.55 ms is observed by photoluminescence decay after the ICP dry etching at −140 °C. This leads to an open‐circuit voltage drop for the (p)a‐Si:H/(n)c‐Si/(n)a‐Si:H heterojunction structure from 680 to 630 mV. A detailed study of the defect properties by deep‐level transient spectroscopy (DLTS), numerical simulation, and its behavior after wet etching and thermal annealing is presented.

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“…It is clear that the R S of our film is 3 to 7 times lower than the calculated values, indicating either a better film quality in our conditions than in previously reported data, a higher doping than expected, or a conduction path in the silicon due to an inversion region. [15] We can notice that the sheet resistance hardly decreases when the thickness increases from 10 to 20 nm. The GaP n-type doping comes from Si diffusion from the substrate which is not optimized yet.…”

Section: Electrical Measurementsmentioning

confidence: 87%