Characterization of electrical linewidth test structures patterned in [100] silicon-on-insulator for use as CD standards

Cresswell, Michael W.; Allen, Richard A.; Ghoshtagore, R. N.; Guillaume, N.M.P.; Shea, Patrick J.; Everist, Sarah C.; Linholm, L.W.

doi:10.1109/icmts.2000.844393

Cited by 3 publications

(2 citation statements)

References 10 publications

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“…The electrical critical dimension (ECD) measurement of the width of features is inherently different from SEM and AFM [7]. Instead of imaging a region of a feature and determining the width from one or more cross-section scans of the images, the ECD is a measure of the average cross-sectional width of a conductive feature.…”

Section: Current Nano-scale Linewidth Measurement Methodsmentioning

confidence: 99%

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A Model for Step Height, Edge Slope and Linewidth Measurements Using AFM

Zhao¹,

Vorburger²,

Fu³

et al. 2003

AIP Conference Proceedings

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Nano-scale linewidth measurements are performed in semiconductor manufacturing and in the data storage industry and will become increasingly important in micro-mechanical engineering. With the development of manufacturing technology in recent years, the sizes of linewidths are steadily shrinking and are in the range of hundreds of nanometers. As a result, it is difficult to achieve accurate measurement results for nanometer scale linewidth, primarily because of the interaction volume of electrons in materials for an SEM probe or the tip size of an AFM probe. However, another source of methods divergence is the mathematical model of the line itself. In order to reduce the methods divergences caused by different measurement methods and instruments for an accurate determination of nanometer scale linewidth parameters, a metrological model and algorithm are proposed for linewidth measurements with AFM. The line profile is divided into 5 parts with 19 sections and 20 key derived points. Each section is fitted by a least squares straight line, so that the profile can be represented by a set of straight lines and 6 special points, or by a 20x2 matrix of fitted points and a 6x2 matrix of starter points. According to the algorithm, W T and W TF , W M and WMF, W B and WBF represent the widths at the top, the middle and the bottom of the line profile before and after the least squares fitting, respectively. A L and A R represent the left and right sidewall angles, and H represents the step height of the line profile. Based on this algorithm, software has been developed using MATLAB for the calculation of width and height parameters of the line profile. A NIST nanometer scale linewidth artifact developed at NIST's Electronics and Electrical Engineering Laboratory (EEEL) was measured using a commercial AFM with nanotube tips. The measured linewidth profiles are analyzed using our model, algorithm and software. The model developed in this paper is straightforward to understand, and provides a common set of parameters to evaluate the nano-scale line feature.

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Section: Current Nano-scale Linewidth Measurement Methodsmentioning

confidence: 99%

“…A NIST prototype nanometer scale linewidth sample developed at NIST's Electronics and Electrical Engineering Laboratory (EEEL) was chosen for experiments [7,13]. This sample is an etched silicon single crystal on an insulating buried oxide [5].…”

Section: Sample and Measurementmentioning

confidence: 99%

A Model for Step Height, Edge Slope and Linewidth Measurements Using AFM

Zhao¹,

Vorburger²,

Fu³

et al. 2003

AIP Conference Proceedings

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Electrical linewidth test structures patterned in [100] silicon-on-insulator for use as CD standards

Cresswell

Bonevich

Allen

et al. 2001

IEEE Trans. Semicond. Manufact.

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SETEC/Semiconductor Manufacturing Technologies Program: 1999 Annual and Final Report

McBrayer¹

2000

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This report summarizes the Manufacturing Technologies results of work conducted by the Semiconductor Program at Sandia National Laboratories (Sandia) during 1999. This work was perfo-med by one working group: the Semiconductor Equipment Technology Center (SETEC). The group's projects included Numerical/Experimental Characterization of the Growth of Single-Crystal Calcium Fluoride (CaFz); The Use of High-Resolution Transmission Electron Microscopy (HRTEM) Imaging for Certifying Critical-Dimension Reference Materials Fabricated with Silicon Micromachining; Assembly Test Chip for Flip Chip on Board; Plasma Mechanism Validation: Modeling and Experimentation; and Model-Based Reduction of Contamination in Gate-Quality Nitride Reactor. During 1999, all projects focused on meeting customer needs in a timely manner and ensuring that projects were aligned with the goals of the National Technology Roadmap for Semiconductors sponsored by the Semiconductor Industry Association and with Sandia's defense mission. This report also provides a short history of the Sandia/SEMATECH relationship and a brief on all projects completed during the seven years of the program. And as such, this is the final report for the Sandia/SEMATECH Cooperative Research and Development Agreement (CRADA), SC92/01082.

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Characterization of electrical linewidth test structures patterned in [100] silicon-on-insulator for use as CD standards

Cited by 3 publications

References 10 publications

A Model for Step Height, Edge Slope and Linewidth Measurements Using AFM

A Model for Step Height, Edge Slope and Linewidth Measurements Using AFM

Electrical linewidth test structures patterned in [100] silicon-on-insulator for use as CD standards

SETEC/Semiconductor Manufacturing Technologies Program: 1999 Annual and Final Report

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