Characterization of $Cdv/dt$ Induced Power Loss in Synchronous Buck DC–DC Converters

Zhao, Qun; Stojcic, G.

doi:10.1109/tpel.2007.900527

Cited by 99 publications

(30 citation statements)

References 8 publications

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“…For high current and high frequency converter, the threshold voltage with V GS at 0 V may be too low. This is because the energy stored in the loop inductance and the dv/dt stress increase with the current [5], [17]. Although V SD is known to increase in accordance with V GS OF F [14]- [16] and consequently dead time losses are expected to increase, this work demonstrates that the application of a negative gate voltage V GS OF F in GaN FETs is more complex.…”

Section: State Of Current Research and Aim Of This Workmentioning

confidence: 90%

Investigation of dead-time behaviour in GaN DC-DC buck converter with a negative gate voltage

Roschatt

McMahon

Pickering

2015

2015 9th International Conference on Power Electronics and ECCE Asia (ICPE-ECCE Asia)

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The low threshold voltage of Gallium Nitride enhancement mode FETs is a concern in high current high frequency synchronous DC-DC buck converters. Applying a negative gate voltage to the low side FET to improve the dV/dt robustness increases the voltage drop between source and drain during dead-time conduction. This has consequences not only on the efficiency, but more importantly on the bootstrap voltage. Even with precise dead-timing, the large voltage drop from drain to source still results in a significant variation of the bootstrap voltage. This results in a change of gate turn on speed and increases the dV/dt stress. The very short dead-time needed to avoid great variations in the bootstrap voltage means that the voltage drop from source to drain can no longer bet treated as a constant as it varies greatly during the dead-time.

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Section: State Of Current Research and Aim Of This Workmentioning

confidence: 90%

Investigation of dead-time behaviour in GaN DC-DC buck converter with a negative gate voltage

Roschatt

McMahon

Pickering

2015

2015 9th International Conference on Power Electronics and ECCE Asia (ICPE-ECCE Asia)

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“…3 [14]- [15]. This paper focuses on the parasitic inductance at the device terminals in order to clarify the false turn on mechanism.…”

Section: Parasitic Parameter Of Power Devicesmentioning

confidence: 99%

An analysis of false turn-on mechanism on power devices

Nishigaki

Umegami

Hattori

et al. 2014

2014 IEEE Energy Conversion Congress and Exposition (ECCE)

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Currently, driving power circuits at high switching frequency is performed in order to downsize and lighten switching power supplies. Along with it, wide band gap semiconductor devices, GaN and SiC, have attracted attention. However, there is a great constrain related to the false turn-on phenomenon produced by gate noise because these wide band gap semiconductor devices have low threshold voltage. If the false turn-on phenomenon occurs, the efficiency of the power supply decreases. Therefore, this paper analyzes the gate noise performance using simulation and experimental tests focusing on the parasitic inductance of the power devices terminals. As a result, it was found that the gate noises can be related to the recovery current of the body diodes. Additionally, this analysis was theorized by the comparison between the experimental results and the theoretical equation using an equivalent circuit.

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“…If it exceeds the threshold voltage, the SyncFET that should remain in offstate will be partially or even fully turned on, which is defined as the spurious turn-on. It can incur substantial drain current, excessive switching losses, self-oscillation and even intermittent shoot-through [1], [7]- [8], which should be prevented to ensure a reliable and efficient operation of the bridge-leg configuration.…”

Section: Nomenclaturementioning

confidence: 99%

New insight into the mechanism of the spurious triggering pulse in the bridge-leg configuration

Wang

Chung

2013

2013 5th International Conference on Power Electronics Systems and Applications(PESA)

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The spurious triggering pulse is an intrinsic feature in the gate-source voltage of the synchronous switch of the bridge-leg configuration. If it exceeds the threshold voltage of the switch, the spurious turn-on will occur and consequently incur excessive switching losses, self-oscillation and even shoot-through. This paper intends to establish a circuit-level analytical model of the synchronous buck converter considering all important parasitic elements and the reverse recovery characteristics of the body diode of the synchronous MOSFET to explore the underlying mechanism of the spurious triggering pulse. It is discovered that apart from the generally acknowledged Cdv/dt induced increase in the gate voltage, the Ldi/dt induced decease in the source voltage contributes to the pulse as well. Besides, the impact of the gate impedance of the synchronous MOSFET on this pulse depends on the dominance of these two factors. The analytical results will be verified by the experimental results of the prototype of a 40V/6A synchronous buck converter. Keywords-MOSFET, spurious turn-on, Cdv/dt induced turn-on, bridge-leg configuration.Nomenclature C gs gate-source capacitance C gd gate-drain capacitance C ds drain-source capacitance L d drain inductance L s source inductance L g gate inductance L ds Total drain and source inductances R g gate drive resistance g fs transconductance V th threshold voltage Q RR reverse recovery charge S snappiness factor M CtrlFET M 2 SyncFET v ds drain-source voltage v gs gate-source voltage v gd gate-drain voltage i ch channel current i d drain current i g gate current i f body diode current I L load current V DD input voltage V GG high gate voltage v Lds voltage across L ds V ds(on) on-state voltage of the MOSFET V Db(on) on-state voltage of the body diode

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Characterization of $Cdv/dt$ Induced Power Loss in Synchronous Buck DC–DC Converters

Cited by 99 publications

References 8 publications

Investigation of dead-time behaviour in GaN DC-DC buck converter with a negative gate voltage

Investigation of dead-time behaviour in GaN DC-DC buck converter with a negative gate voltage

An analysis of false turn-on mechanism on power devices

New insight into the mechanism of the spurious triggering pulse in the bridge-leg configuration

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