2015 9th International Conference on Power Electronics and ECCE Asia (ICPE-ECCE Asia) 2015
DOI: 10.1109/icpe.2015.7167910
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Investigation of dead-time behaviour in GaN DC-DC buck converter with a negative gate voltage

Abstract: The low threshold voltage of Gallium Nitride enhancement mode FETs is a concern in high current high frequency synchronous DC-DC buck converters. Applying a negative gate voltage to the low side FET to improve the dV/dt robustness increases the voltage drop between source and drain during dead-time conduction. This has consequences not only on the efficiency, but more importantly on the bootstrap voltage. Even with precise dead-timing, the large voltage drop from drain to source still results in a significant … Show more

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Cited by 11 publications
(7 citation statements)
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References 11 publications
(9 reference statements)
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“…10) due to driver delay and this dead time is enough for GaN transistor switching transitions. The impact of dead time on the efficiency of GaN transistors is also analysed in [4], [6], [7], [16]. In the literature, it is proposed to use 0 ns dead time for switching on and about 30 ns dead time for switching off, but the analysis is provided for driver with 0V turn off voltage.…”
Section: The Experimental Results and Discussionmentioning
confidence: 99%
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“…10) due to driver delay and this dead time is enough for GaN transistor switching transitions. The impact of dead time on the efficiency of GaN transistors is also analysed in [4], [6], [7], [16]. In the literature, it is proposed to use 0 ns dead time for switching on and about 30 ns dead time for switching off, but the analysis is provided for driver with 0V turn off voltage.…”
Section: The Experimental Results and Discussionmentioning
confidence: 99%
“…This voltage drop decreases efficiency of the converter; therefore, large negative voltage is not desirable. Even with precise dead-timing, the large voltage drop from drain to source still results in a significant variation of the bootstrap voltage [4]; therefore, bootstrap voltage source for driver is not preferable in this case.…”
Section: Gate Driver Designmentioning
confidence: 99%
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“…One of the main differences in terms of the gate control is the gate threshold voltage V GS(th), the gate plateau and the maximum gate voltage V GS(max). The maximum gate voltage V GS is much lower than in Si MOSFETs, but anyway most GaN transistors are not fully turned on until V GS reaches about 4 V [29]. To turn off the GaN transistor, the gate voltage must be kept below the minimum gate threshold voltage, which is 1.3 V in this case.…”
Section: Design Of Gan Transistor Based Full Bridge High Frequency Inmentioning
confidence: 99%
“…However, the optimum dead-time for GaN transistors changes with the converter output power and input DC-link voltage [8]. An in-depth investigation in [9] shows the need to modify both the rising and falling edges of the microcontroller (MCU) control signal with the variable dead-time.…”
Section: Introductionmentioning
confidence: 99%