Characterization of a thick copper pillar bump process

Flack, Warren W.; Nguyen, Ha-Ai; Capsuto, Elliott Sean; McEwen, C.D.

doi:10.1109/isapm.2007.4419942

Cited by 11 publications

(9 citation statements)

References 3 publications

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“…With advancements in integration of multiple chips on a single package, the requirements of I/O densities for these chips has far exceeded the density and pitch capabilities provided by the traditional solder bump processes [4,5]. As a result, the industry has adopted pillar bumps to replace these solder bumps as they enable smaller pitches, better electromigration performance and better thermal regulation [6][7][8]. These pillar bumps are fabricated using the electroplating process with 40-50 μm widths and a maximum height to width aspect ratio of 2 [9].…”

Section: Introductionmentioning

confidence: 99%

Single shot, large area metal sintering with micrometer level resolution

et al. 2018

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This paper presents the optics design for a microscale Selective Laser Sintering (μ-SLS) system that aims to allow large areas of nanoparticles to be sintered simultaneously while still maintaining micrometer scale feature resolutions in order to improve the throughput of the microscale additive manufacturing process. The optics design is shown to be able to sinter a 2.3 mm by 1.3 mm area of metal nanoparticles that have been spread into a ~400 nm thick layer with a feature resolution of ~3 μm in a single shot. The optical resolution of this system is shown to be ~1.2 μm indicating that only about 2-3 pixels are needed to form a good sintered part. In addition, using the optical design presented in this paper, it is estimated that the μ-SLS system should be able to achieve a volumetric throughput of ~63 mm 3 /hr, making this process one of the highest throughput processes available today for the microscale additive manufacturing of three-dimensional metal structures.

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Section: Introductionmentioning

confidence: 99%

Single shot, large area metal sintering with micrometer level resolution

et al. 2018

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“…As an alternative to solder bumps, Cu-pillars have been suggested, pitch arrays and higher integration densities (Flack et al, 2007). Therefore, Cu-pillars are more reliable than solder bumps (Ebersberger and Lee, 2008).…”

Section: Introductionmentioning

confidence: 99%

“…Furthermore, the larger yield stress, and Young’s modulus of Cu can provide better mechanical and thermal performance (Lu and Wong, 2009). During the reflow process, solder bumps are prone to collapse, while Cu pillars keep their shape in all directions, allowing finer pitch arrays and higher integration densities (Flack et al , 2007). Therefore, Cu-pillars are more reliable than solder bumps (Ebersberger and Lee, 2008).…”

Section: Introductionmentioning

confidence: 99%

“…The IMC is very sensitive under the high current stress conditions experienced during electromigration studies, posing great reliability concerns on electronic devices. Furthermore, better control of the parameters, such as bonding temperature and pressure, is demanded for smaller and finer-pitch pillars (Flack et al , 2007, Jeong et al , 2012). An excessive bonding pressure will lead to the squeezing out of melted Sn from the interface with Cu pillars, which can result in short-circuit failure if the pitch between the adjacent pillars is very small (Jeong et al , 2012).…”

Section: Introductionmentioning

confidence: 99%

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Fabrication and characterization of Cu-Sn-Ni-Cu interconnection microstructure for electromigration studies in 3D integration

Xiao

Munief

et al. 2016

SSMT

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2016),"Thermo-mechanical challenges of reflowed lead-free solder joints in surface mount components: a review", Soldering & Surface Mount Technology, Vol. 28 Iss 2 pp. 41-62 http://dx.If you would like to write for this, or any other Emerald publication, then please use our Emerald for Authors service information about how to choose which publication to write for and submission guidelines are available for all. Please visit www.emeraldinsight.com/authors for more information. About Emerald www.emeraldinsight.comEmerald is a global publisher linking research and practice to the benefit of society. The company manages a portfolio of more than 290 journals and over 2,350 books and book series volumes, as well as providing an extensive range of online products and additional customer resources and services.Emerald is both COUNTER 4 and TRANSFER compliant. The organization is a partner of the Committee on Publication Ethics (COPE) and also works with Portico and the LOCKSS initiative for digital archive preservation. AbstractPurpose -The purpose of this paper is to fabricate a new Cu-Sn-Ni-Cu interconnection microstructure for electromigration studies in 3D integration. Design/methodology/approach -The Cu-Sn-Ni-Cu interconnection microstructure is fabricated by a three-mask photolithography process with different electroplating processes. This microstructure consists of pads and conductive lines as the bottom layer, Cu-Sn-Ni-Cu pillars with the diameter of 10-40 m as the middle layer and Cu conductive lines as the top layer. A lift-off process is adopted for the bottom layer. The Cu-Sn-Ni-Cu pillars are fabricated by photolithography with sequential electroplating processes. To fabricate the top layer, a sputtered Cu layer is introduced to prevent the middle-layer photoresist from being developed. With the final Cu electroplating processes, the Cu-Sn-Ni-Cu interconnection microstructure is successfully achieved. Findings -The surface morphology of Cu-Sn pillars consists of densely packed clusters which are formed by an ordered arrangement of tetragonal Sn grains. The diffusion of Cu atoms into the Sn phases is observed at the Cu/Sn interface. Furthermore, the obtained Cu-Sn-Ni-Cu pillars have a flat surface with an average roughness of 13.9 nm. In addition, the introduction of Ni layer between the Sn and the top Cu layers in the Cu-Sn-Ni-Cu pillars can mitigate the diffusion of Cu atoms into Sn phases. The process is verified by checking the electrical performance using four-point probe measurements. Originality/value -The method described in this paper which combined a three-mask photolithography process with sequential Cu, Sn, Ni and Cu electroplating processes provides a new way to fabricate the interconnection microstructure for future electromigration studies.

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“…Copper pillar bumps were first introduced into production by Intel 65-nm technology in 2006 [1]. The advantages are in higher interconnect densities, higher reliability, improved electrical and thermal performances with the potential for lead-free bump implementation [2]. The electroplating is by far the most commercially viable of copper pillar bumps fabrication.…”

Section: Introdutionmentioning

confidence: 99%

High Coplanarity and Fine Pitch Copper Pillar Bumps Fabrication Method

Huang

Hsu

Lee

et al. 2010

Jpn. J. Appl. Phys.

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In this paper, we report a novel plating-friendly polishing mechanism for fabrication of high coplanarity and high density lead-free copper pillar bumps for advanced packaging applications. The final experimental results showed that the uniformity in wafer (UIW) could be sharply improved from 4.31% after plating to 2.88% after polishing and even to 2.54% after reflow throughout the entire 4 inch wafer.

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Characterization of a thick copper pillar bump process

Cited by 11 publications

References 3 publications

Single shot, large area metal sintering with micrometer level resolution

Single shot, large area metal sintering with micrometer level resolution

Fabrication and characterization of Cu-Sn-Ni-Cu interconnection microstructure for electromigration studies in 3D integration

High Coplanarity and Fine Pitch Copper Pillar Bumps Fabrication Method

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