2010
DOI: 10.1143/jjap.49.06gn07
|View full text |Cite
|
Sign up to set email alerts
|

High Coplanarity and Fine Pitch Copper Pillar Bumps Fabrication Method

Abstract: In this paper, we report a novel plating-friendly polishing mechanism for fabrication of high coplanarity and high density lead-free copper pillar bumps for advanced packaging applications. The final experimental results showed that the uniformity in wafer (UIW) could be sharply improved from 4.31% after plating to 2.88% after polishing and even to 2.54% after reflow throughout the entire 4 inch wafer.

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
2

Citation Types

0
1
0

Year Published

2015
2015
2024
2024

Publication Types

Select...
2

Relationship

0
2

Authors

Journals

citations
Cited by 2 publications
(3 citation statements)
references
References 7 publications
0
1
0
Order By: Relevance
“…The prepared bumps have a regular morphology, and there are no impurities and voids inside the bumps, which confirms that it is a feasible and practical approach [6]. Unfortunately, previous studies have not investigated the uniformity of bump arrays, and the existing studies on bump consistency have concentrated on large-feature-sizes and low-density bump arrays [3,4,7], leaving much space for exploration of small-dimension bump arrays with pith inside 10 μm. Besides, there are several urgent concerns during the fabrication process, such as skip plating, hydrogen bubble entrapment, and nodular growth, which will be discussed in detail in the subsequent chapter.…”
Section: Introductionmentioning
confidence: 58%
See 1 more Smart Citation
“…The prepared bumps have a regular morphology, and there are no impurities and voids inside the bumps, which confirms that it is a feasible and practical approach [6]. Unfortunately, previous studies have not investigated the uniformity of bump arrays, and the existing studies on bump consistency have concentrated on large-feature-sizes and low-density bump arrays [3,4,7], leaving much space for exploration of small-dimension bump arrays with pith inside 10 μm. Besides, there are several urgent concerns during the fabrication process, such as skip plating, hydrogen bubble entrapment, and nodular growth, which will be discussed in detail in the subsequent chapter.…”
Section: Introductionmentioning
confidence: 58%
“…IOP Publishing doi:10.1088/1742-6596/2783/1/012022 2 High-uniformity bump arrays are essential for bonding yields and display device quality, and current procedures for preparing Micro-LED bumps include electroplating [3], evaporation [4], and electroless plating [5]. Electroplating is an electrochemical process that requires the introduction of current during the preparation process.…”
Section: Introductionmentioning
confidence: 99%
“…Recently, copper pillar bump technology is receiving great attention for flip chip package as well as other advanced packaging methods due to their many advantageous features such as lower joint resistance, better electromigration resistance, higher I/O density, finer pitch, and better thermal dissipation than solder bumps. [1][2][3] Copper pillar bump is composed of copper pillar and solder cap. Copper pillar connects solder with under bump metallurgy (UBM) and chip pad.…”
mentioning
confidence: 99%