This paper presents a novel class of miniature fluxgate magnetometers fabricated on a print circuit board (PCB) substrate and electrically connected to each other similar to the current “flip chip” concept in semiconductor package. This sensor is soldered together by reversely flipping a 5 cm × 3 cm PCB substrate to the other identical one which includes dual magnetic cores, planar pick-up coils, and 3-D excitation coils constructed by planar Cu interconnections patterned on PCB substrates. Principles and analysis of the fluxgate sensor are introduced first, and followed by FEA electromagnetic modeling and simulation for the proposed sensor. Comprehensive characteristic experiments of the miniature fluxgate device exhibit favorable results in terms of sensitivity (or “responsivity” for magnetometers) and field noise spectrum. The sensor is driven and characterized by employing the improved second-harmonic detection technique that enables linear V-B correlation and responsivity verification. In addition, the double magnitude of responsivity measured under very low frequency (1 Hz) magnetic fields is experimentally demonstrated. As a result, the maximum responsivity of 593 V/T occurs at 50 kHz of excitation frequency with the second harmonic wave of excitation; however, the minimum magnetic field noise is found to be 0.05 nT/Hz1/2 at 1 Hz under the same excitation. In comparison with other miniature planar fluxgates published to date, the fluxgate magnetic sensor with flip chip configuration offers advances in both device functionality and fabrication simplicity. More importantly, the novel design can be further extended to a silicon-based micro-fluxgate chip manufactured by emerging CMOS-MEMS technologies, thus enriching its potential range of applications in modern engineering and the consumer electronics market.

A new class of tri-axial miniature magnetometer consisting of a planar fluxgate structure with an orthogonal ferromagnetic fluxguide centrally situated over the magnetic cores is presented. The magnetic sensor possesses a cruciform ferromagnetic core placed diagonally upon the square excitation coil under which two pairs of pick-up coils for in-plane field detection are allocated. Effective principles and analysis of the magnetometer for 3-D field vectors are described and verified by numerically electromagnetic simulation for the excitation and magnetization of the ferromagnetic cores. The sensor is operated by applying the second-harmonic detection technique that can verify V-B relationship and device responsivity. Experimental characterization of the miniature fluxgate device demonstrates satisfactory spatial magnetic field detection results in terms of responsivity and noise spectrum. As a result, at an excitation frequency of 50 kHz, a maximum in-plane responsivity of 122.4 V/T appears and a maximum out-of-plane responsivity of 11.6 V/T is obtained as well. The minimum field noise spectra are found to be 0.11 nT/√Hz and 6.29 nT/√Hz, respectively, in X- and Z-axis at 1 Hz under the same excitation frequency. Compared with the previous tri-axis fluxgate devices, this planar magnetic sensor with an orthogonal fluxguide provides beneficial enhancement in both sensory functionality and manufacturing simplicity. More importantly, this novel device concept is considered highly suitable for the extension to a silicon sensor made by the current CMOS-MEMS technologies, thus emphasizing its emerging applications of field detection in portable industrial electronics.

We demonstrate that the work function of a metal gate can be vaned by inserting a very thin metal layer ("Metal A") between a thick metal ("Metal B") and the gate dielectric. The flat band voltage (VpB) of the MOS (metaloxide-semiconductor) capacitor structure can he controlled within the range bounded by Metal A and Metal B individually, as demonstrated with various stacked bimetal layers. For continuous thin layers, we speculate that the work function tunability may be due to the drastic change of the electron density in the thin continuous metal layer in direct contact with a bulk metal. This drastic change of electron density results in a larger junction depth than that expected for B bulk metal. Non-uniform thin layers also appear effective for workfunction tuning as well, and the observed VFB shift is attributed to the metal island formation at the dielectnc/Metal A interface. IntroductionConventional poly Si gate technology has faced several challenging issues due to poly-depletion and B penetration. Recently, the "dual metal gate" approach has attracted attention to improve CMOS performance, as opposed to mid-gap metals, such as TiN and TaN. For CMOS integration, metals with "tunable" workfunctions may be suitable for metal gate applications. Various alloy systems, such as metal alloys (RufTa)[l], silicides (NiSi)[2] and nitndes (MoN)[3], have been investigated for work function "tunability". Both alloying and implantation are being considered as possible techniques to tune the metal gate work function.Recently, another approach has been suggested by several groups using stacked metal layers as the electrode for a MOS (metal-oxide-semiconductor) system for tuning the flat band voltage (work function). Ciao et al. reported work function tuning of a dual metal gate stack using AVTaN bimetal layers deposited by sputtering [4]. Olsen et al. have also demonstrated work function tunability of 0.1V by changing the TaN thickness from 40A to 808, in the TdTaN/HfO2/Si MOS structure. [5] In this work, we systematically examine the workfunction tunability of bilayer metal gate electrodes. ExperimentalA schematic cross-sectional view of OUI capacitors is shown in Fig. 1. The gate metal stack consists of a very thin bottom metal layer on the gate dielectric (Metal A) and a thick capping metal layer (Metal B). The thickness of Metal A was vaned in the target range of 58, to IOOA, utilizing a quartz-crystal microbalance that intercepted the flux in theebeam deposition chamber. A stacked MOS capacitor was fabricated to obtain the flat hand voltage (VFB) behavior. The bi-metal/Si02/Si MOS structure was fabricated in the following sequential manner. A gate dielectric (44 8, thick thermal Si02 film) was formed on HF-last prepared, n-type Si(100) (I-IOOcm). The bimetal layers were then sequentially deposited by e-beam evaporation, without breaking vacuum, and with no intentional substrate heating in order to minimize interfacial alloying between the metals. The pressure was maintained at 6 -8~1 0 .~ Torr during deposition an...

We have investigated the effects of gate-first and gate-last process on oxide/InGaAs interface quality using In0.53Ga0.47As metal-oxide-semiconductor capacitors (MOSCAPs) with atomic-layer-deposited (ALD) oxides. Sequence of source/drain activation anneal in the process results in remarkable electrical and physical difference. Applying gate-last process provides significant frequency dispersion reduction and interface trap density reduction for InGaAs MOSCAPs compared to gate-first process. A large amount of In–O, Ga–O, and As–As bonds was observed on InGaAs surface after gate-first process while no detectable interface reaction after gate-last process. Electrical and physical results also show that ALD Al2O3 exhibits better interface quality on InGaAs than HfO2.

This paper presents a series of processes for fabricating lead-zirconate-titanate (PZT) microstructures on a silicon substrate. An aerosol deposition method was used to deposit PZT thick film at room temperature. The low temperature deposition enabled a special lift-off process for patterning thick PZT films using a THB-151N photoresist. The milling rate of THB-151N by PZT particles was found to be the same as the PZT deposition rate of 5 µm h −1 . Using this patterning technique, complex configurations of PZT microstructures have been demonstrated. Suspended multi-layer PZT microstructures have also been realized in this work.