Characterization of a commercial 65 nm CMOS technology for SLHC applications

Bonacini, S.; Valerio, P.; Avramidou, R.; Ballabriga, R.; Faccio, F.; Kloukinas, K.; Marchioro, A.

doi:10.1088/1748-0221/7/01/p01015

Cited by 58 publications

(36 citation statements)

References 6 publications

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“…It offers about four times higher logic density compared to the 130 nm node and has recently been radiation qualified by CERN [82]. It is found not to require special layout of transistors in digital functions to tolerate the HL-LHC radiation environment.…”

Section: A41 Readout Chip Technologymentioning

confidence: 99%

CMS Technical Design Report for the Pixel Detector Upgrade

Dominguez¹

2012

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The original design goal of the LHC was to operate at 1 × 10 34 cm -2 s -1 with 25 ns bunch spacing, where approximately 25 simultaneous inelastic collisions per crossing ("pile-up") occur. With the upgrade of the accelerators, the luminosity and pile-up will more than double. The current pixel detector is crucial to charged particle tracking, but was not designed to perform effectively in such collision conditions and the physics program of CMS would suffer as a result. We propose to replace the current pixel tracker with a new high efficiency and low mass detector with four barrel layers and three forward/backward disks to provide four-hit pixel coverage out to pseudorapidities of ±2.5. This new detector will meet or exceed the original design specifications in these high luminosity environments. In this report, we provide details on the design, construction and installation of the upgraded pixel detector as well as estimates of its expected performance. Cover Design S. Cittolin AcknowledgmentsWe would like to thank the technical staff from the various institutions for the design, R&D and testing of the many components of this upgrade.We also wish to thank the LHCC for their oversight and crucial advice during the development of the the pixel upgrade project. The important feedback from following CMS internal reviewers greatly helped in the development of this technical design report: D. Contardo, S. Dasu, S.C. Eno, P. Giacomelli, G. Gomez Ceballos, E. Halkiadakis, C. Hill, M. Klute, S. Lowette, M. Mannelli, S. Nahn, I. Shipsey, D. Stuart, S. Tkaczyk and J. Varela.A special thanks goes to the CMS Secretariat, in particular Anastasia Dolya, for their tireless support during all stages of the project. We also acknowledge the warm support received from the CMS management team and computing project.Finally, we dedicate this technical design report for the upgrade of the pixel detector to the memory of our two colleagues and friends:

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Section: A41 Readout Chip Technologymentioning

confidence: 99%

CMS Technical Design Report for the Pixel Detector Upgrade

Dominguez¹

2012

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“…This was confirmed for MOS transistors when they became available with these thin oxides more than a decade later [8]. Now it is common knowledge that transistors of commercial deep submicron CMOS technologies withstand very significant total For instance, in [9] the PMOS of minimum size shows significant current drive degradation which cannot be attributed to its radiation induced threshold voltage shift alone.…”

Section: Charge Collection Mechanism By Drift and Deep Submicron Cmosmentioning

confidence: 84%

CMOS monolithic active pixel sensors for high energy physics

Snoeys¹

2014

Nuclear Instruments and Methods in Physics Research Section A:

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a b s t r a c tMonolithic pixel detectors integrating sensor matrix and readout in one piece of silicon are only now starting to make their way into high energy physics. Two major requirements are radiation tolerance and low power consumption. For the most extreme radiation levels, signal charge has to be collected by drift from a depletion layer onto a designated collection electrode without losing the signal charge elsewhere in the in-pixel circuit. Low power consumption requires an optimization of Q/C, the ratio of the collected signal charge over the input capacitance [1]. Some solutions to combine sufficient Q/C and collection by drift require exotic fabrication steps. More conventional solutions up to now require a simple in-pixel readout circuit. Both high voltage CMOS technologies and Monolithic Active Pixel Sensors (MAPS) technologies with high resistivity epitaxial layers offer high voltage diodes. The choice between the two is not fundamental but more a question of how much depletion can be reached and also of availability and cost. This paper tries to give an overview.

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“…This curve is compared in figure 6 with the cross section (evaluated in a previous study [6]) of a standard library flip-flop in the same …”

Section: B Seu Sensitivity Resultsmentioning

confidence: 99%

“…Previous studies [6] suggested this value as the minimum needed to assure acceptable performances degradation due to TID in the used 65-nm technology. A more detailed description of the test chip and its components can be found in [8].…”

Section: The Serializersmentioning

confidence: 99%

“…These very promising results are, however, not enough to validate these two blocks to be used in the LPGBT, and a characterization of the radiation effects is required. These effects include high Single Event Upset (SEU) rates [4], [5], that generate temporary malfunctioning, and the Total Ionizing Dose (TID) effects, which can cause permanent faults [3], [6]. The maximum tolerable error rate is only 1 wrong word transmitted per 24 hours of operation, i.e.…”

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confidence: 99%

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Characterization of low power radiation-hard reed-solomon code protected serializers in 65-nm for HEP experiments electronics

Felici

Bonacini

Ottavi

2015

2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)

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The availability of low-power, radiation-resistant components has an enormous importance in the development of the electronic systems for modern detectors in a High Energy Physics (HEP) experiment. This paper describes the characterization in terms of radiation effects of two serializer blocks within a high speed transmitter, prior developed with the objective of achieving a power consumption of less than 30 mW at the operating speed of 4.8 Gbit/sec. Within the first serializer, called “simple TMR”, a traditional solution, based on the hardware redundancy, has been implemented. In the second case a new architecture, less power consuming, called “code protected”, has been proposed. The tests previously performed shown an average consumption of ~30 mW and ~19 mW, respectively, for a bit rate of 4.8 Gbit/sec but do not fully clarify if the blocks are suitable for working under extremely high radiation levels. Hence, a deep radiation hardness investigation has been performed and presented here to confirm the availability of these blocks in a HEP electronic system. SEU sensitivities are measured and bit error rates better than 2 E-15 are obtained, confirming that the “code protected” solution assures reliable communications in HEP experiments environment with a smaller power consumption. These blocks have also been designed and tested to cope with a total ionizing dose of 100 Mrad over 10 years of operation

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Characterization of a commercial 65 nm CMOS technology for SLHC applications

Cited by 58 publications

References 6 publications

CMS Technical Design Report for the Pixel Detector Upgrade

CMS Technical Design Report for the Pixel Detector Upgrade

CMOS monolithic active pixel sensors for high energy physics

Characterization of low power radiation-hard reed-solomon code protected serializers in 65-nm for HEP experiments electronics

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