Characterization and modeling of solder balls and through-strata-vias (TSVs) in 3D architecture

Xu, Zheng; Beece, Adam; Zhang, Dingyou; Chen, Qianwen; Rose, Kenneth; Lu, Jian‐Qiang

doi:10.1109/epeps.2010.5642538

Cited by 15 publications

(4 citation statements)

References 3 publications

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“…A key component in 3D integration technology is the throughsilicon-via (TSV), which electrically connects multiple strata of ICs vertically, enabling high-performance, highfunctionality, compact heterogeneous systems with high data bandwidth and speed, and low power and cost. Substantial research is being conducted on other aspects of TSVs, such as design and processing development [1][2][3][4][5][6][7][8][9]. The objective of this paper is to investigate thermal-mechanical failure mechanisms of TSV-based 3D interconnect structures.…”

Section: Introductionmentioning

confidence: 99%

Backside TSV protrusion induced by thermal shock and thermal cycling

Zhang

Hummler²,

Smith³

et al. 2013

2013 IEEE 63rd Electronic Components and Technology Conference

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This paper reports on thermal-mechanical failures of through-silicon-vias (TSVs), in particular, for the first time, the protrusions at the TSV backside, which is exposed after wafer bonding, thinning and TSV revealing. Temperature dependence of TSV protrusion is investigated based on widerange thermal shock and thermal cycling tests. While TSV protrusion on the TSV frontside is not visible after any of the tests, protrusions on the backside are found after both thermal shock tests and thermal cycling tests at temperatures above 250 o C. The average TSV protrusion height increases from ~0.1 μm at 250 ºC to ~0.5 μm at 400 ºC and can be fitted to an exponential function with an activation energy of ~0.6eV, suggesting a Cu grain boundary diffusion mechanism.

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Section: Introductionmentioning

confidence: 99%

Backside TSV protrusion induced by thermal shock and thermal cycling

Zhang

Hummler²,

Smith³

et al. 2013

2013 IEEE 63rd Electronic Components and Technology Conference

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“…For example, in [7]- [9], the crosstalk between TSVs is analyzed and it is suppressed by introducing a guard ring. In [10]- [13], TSV shielding arrays reduce the coupling, and consequently, the crosstalk is reduced. In [14]- [17], guard ring is used to protect the sensitive active circuits from the TSV coupling noise.…”

Section: Introductionmentioning

confidence: 99%

Partial Coaxial Through-Silicon via for Suppressing the Substrate Noise in 3-Dimensional Integrated Circuit

Zhang

Yao³

2019

IEEE Access

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In this paper, a novel through-silicon via (TSV) structure, named partial coaxial TSV (PC-TSV), is proposed to suppress TSV-induced substrate noise. In this structure, the via is surrounded by a benzocyclobutene (BCB) layer, and a grounded metal ring placed at one end. The BCB layer can effectively reduce the leakage of the signal to the substrate, and the metal ring provides a low impedance path for the substrate noise. An equivalent RLGC model of this structure is also established, and it is verified by simulated result from CST. Then, the performance of PC-TSV is compared with that of the traditional TSV, TSV with p+ layer, and TSV with p+ guard ring. Analysis results in frequency domain indicate PC-TSV has a larger |S 21 | and less near-end crosstalk than other three structures. Additionally, analysis results in time domain show that the substrate voltage noise of this structure is obviously reduced compared with the TSV with p+ layer and TSV with p+ guard ring. Also, a feasible process flow for this structure is given and it is simpler than that for traditional coaxial TSV. INDEX TERMSCrosstalk, equivalent RLGC model, forward transmission coefficient, noise, through-silicon via.

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“…A key component in 3D integration technology is the through‐silicon via (TSV), which electrically connects multiple strata of ICs vertically, enabling high‐performance, high functionality, compact heterogeneous systems with high data bandwidth and speed, and low power and low cost. Substantial research is being conducted on other aspects of TSVs, such as the design [4, 5], processing materials [6], metrology development [7, 8] and thermal–mechanical reliability [9]. The objective of this Letter is to investigate a new type of defect discovered during TSV process integration and manufacturing.…”

Section: Introductionmentioning

confidence: 99%

BMD impact on silicon fin defect at TSV bottom

et al. 2014

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A new type of through‐silicon via (TSV) defect, silicon fin defect, which was found after the TSV deep‐reactive‐ion‐etching process at the TSV bottom is reported. These defects are considered killer TSV defects that may cause process or mechanical failures and have to be eliminated. A scanning electron microscope automatic process inspection approach, which is non‐destructive and proven to be effective, has been established to image the fin defects at the bottom of the trench. A possible root cause of this defect is also explored. Both simulation and benchmarking test results indicate that bulk micro defects (BMDs) in the silicon substrate could serve as a micro‐mask during etching and result in silicon fin defects.

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Characterization and modeling of solder balls and through-strata-vias (TSVs) in 3D architecture

Cited by 15 publications

References 3 publications

Backside TSV protrusion induced by thermal shock and thermal cycling

Backside TSV protrusion induced by thermal shock and thermal cycling

Partial Coaxial Through-Silicon via for Suppressing the Substrate Noise in 3-Dimensional Integrated Circuit

BMD impact on silicon fin defect at TSV bottom

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