Characteristics of SONOS-Type Flash Memory With <i>In Situ</i> Embedded Silicon Nanocrystals

Chiang, Tsung‐Yu; Wu, Yihong; Cheng-Yu, William; Kuo, Po-Yi; Wang, Kuan-Ti; Liao, Chien Chang; Yeh, Chih-Ting; Yang, Wen−Luh; Chao, Tien−Sheng

doi:10.1109/ted.2010.2051489

Cited by 10 publications

(4 citation statements)

References 33 publications

(17 reference statements)

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“…As a strong candidate of computing in memory, Si-based 3D NAND flash with high density, a large on/off current ratio, and perfect compatibility with CMOS technology is in high demand [ 1 , 2 , 3 ]. Among the candidates of 3D NAND flash memory, nanocrystalline silicon (nc-Si) floating-gate memory is considered to be promising due to its low power, fast program and erase speed, and high durability [ 4 , 5 , 6 , 7 , 8 ]. In particular, its high compatibility with modern microelectronics technology is beneficial to be integrated with computing in a memory chip.…”

Section: Introductionmentioning

confidence: 99%

“…In particular, its high compatibility with modern microelectronics technology is beneficial to be integrated with computing in a memory chip. To make nc-Si floating-gate memory truly useable in 3D NAND flash memory, the increase in the injection charge density and the retention characteristic has been always a concern of the industry [ 7 , 8 ]. As for the research progress of floating-gate memory based on Ge nanocrystalline dots, R. Bar et al reported that the memory window of multilayer Ge nanocrystalline floating-gate memory increases from 4.4 to 6.4 V as the number of Ge nanocrystal layers increases from 1 to 5.…”

Section: Introductionmentioning

confidence: 99%

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3D NAND Flash Memory Based on Double-Layer NC-Si Floating Gate with High Density of Multilevel Storage

Shen

et al. 2022

Nanomaterials

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As a strong candidate for computing in memory, 3D NAND flash memory has attracted great attention due to the high computing efficiency, which outperforms the conventional von-Neumann architecture. To ensure 3D NAND flash memory is truly integrated in the computing in a memory chip, a new candidate with high density and a large on/off current ratio is now urgently needed. Here, we first report that 3D NAND flash memory with a high density of multilevel storage can be realized in a double-layered Si quantum dot floating-gate MOS structure. The largest capacitance–voltage (C-V) memory window of 6.6 V is twice as much as that of the device with single-layer nc-Si quantum dots. Furthermore, the stable memory window of 5.5 V can be kept after the retention time of 105 s. The obvious conductance–voltage (G-V) peaks related to the charging process can be observed, which further confirms that the multilevel storage can be realized in double-layer Si quantum dots. Moreover, the on/off ratio of 3D NAND flash memory with a nc-Si floating gate can reach 104, displaying the characteristic of a depletion working mode of an N-type channel. The memory window of 3 V can be maintained after 105 P/E cycles. The programming and erasing speed can arrive at 100 µs under the bias of +7 V and −7 V. Our introduction of double-layer Si quantum dots in 3D NAND float gating memory supplies a new way to the realization of computing in memory.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

3D NAND Flash Memory Based on Double-Layer NC-Si Floating Gate with High Density of Multilevel Storage

Shen

et al. 2022

Nanomaterials

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“…Metal NP embedded devices for charge storage characteristics are commonly exploited in flash memory technology and are typically characterized by capacitance-voltage measurements [1]. On the other hand, increased performance thin-film transistors (TFTs) are commonly fabricated by using metal NPs with complementary metal-oxide-semiconductors (CMOS) and silicon-oxide-nitride-oxidesilicon(SONOS) [11,20]. To fabricate high-performance thin-film semiconductor/gate dielectric stacks such as (ZnO, TiO 2 )/(Al 2 O 3 , HfO 2 ), films were directly deposited on heavily doped substrates via ALD [16][17][18].…”

Section: Introductionmentioning

confidence: 99%

Utilizing embedded ultra-small Pt nanoparticles as charge trapping layer in flashristor memory cells

Orak

Eren

Bıyıklı

et al. 2019

Applied Surface Science

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In this study, a methodology for producing highly controlled and uniformly dispersed metal nanoparticles were developed by atomic layer deposition (ALD) technique. All-ALD grown thin film flash memory (TFFM) cells and their applications were demonstrated with ultra-small platinum nanoparticles (Pt-NPs) as charge trapping layer and control tunnel oxide layer. The ultra-small Pt-NPs possessed sizes ranging from 2.3 to 2.6 nm and particle densities of about 2.5 × 10 13 cm -b . The effect of Pt-NPs embedded on the storage layer for charging was investigated. The charging effect of ultra-small Pt-NPs the storage layer was observed using the electrical characteristics of TFFM. The Pt-NPs were observed by a high-resolution scanning electron microscopy (HR-SEM). The memory effect was manifested by hysteresis in the I DS -V DS and I DS -V GS curves. The charge storage capacity of the TFFM cells demonstrated that ALD-grown Pt-NPs in conjunction with ZnO layer can be considered as a promising candidate for memory devices. Moreover, ZnO TFFM showed a I ON /I OFF ratio of up to 52 orders of magnitude and its threshold voltage (V th ) was approximately −4.1 V using I ds −a/b -V gs curve. Fabricated TFFMs exhibited clear pinch-off and show n-type field effect transistor (FET) behavior. The role of atomic-scale controlled Pt-NPs for improvement of devices were also discussed and they indicated that ALD-grown Pt-NPs can be utilized in nanoscale electronic devices as alternative quantum dot structures.

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“…Moreover, several studies have presented various types of high- k dielectric trapping layers as potential candidates for replacing Si 3 N 4 to provide discrete NVM charge storage [11,12,13,14,15,16]. Furthermore, high- k dielectric materials can improve the gate capacitance, and maintain an equivalent potential difference for a greater thickness compared with SiO 2 .…”

Section: Introductionmentioning

confidence: 99%

Work Function Adjustment by Using Dipole Engineering for TaN-Al2O3-Si3N4-HfSiOx-Silicon Nonvolatile Memory

Lin

Yang

2015

Materials

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This paper presents a novel TaN-Al2O3-HfSiOx-SiO2-silicon (TAHOS) nonvolatile memory (NVM) design with dipole engineering at the HfSiOx/SiO2 interface. The threshold voltage shift achieved by using dipole engineering could enable work function adjustment for NVM devices. The dipole layer at the tunnel oxide–charge storage layer interface increases the programming speed and provides satisfactory retention. This NVM device has a high program/erase (P/E) speed; a 2-V memory window can be achieved by applying 16 V for 10 μs. Regarding high-temperature retention characteristics, 62% of the initial memory window was maintained after 103 P/E-cycle stress in a 10-year simulation. This paper discusses the performance improvement enabled by using dipole layer engineering in the TAHOS NVM.

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Characteristics of SONOS-Type Flash Memory With In Situ Embedded Silicon Nanocrystals

Cited by 10 publications

References 33 publications

3D NAND Flash Memory Based on Double-Layer NC-Si Floating Gate with High Density of Multilevel Storage

3D NAND Flash Memory Based on Double-Layer NC-Si Floating Gate with High Density of Multilevel Storage

Utilizing embedded ultra-small Pt nanoparticles as charge trapping layer in flashristor memory cells

Work Function Adjustment by Using Dipole Engineering for TaN-Al2O3-Si3N4-HfSiOx-Silicon Nonvolatile Memory

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