Work Function Adjustment by Using Dipole Engineering for TaN-Al2O3-Si3N4-HfSiOx-Silicon Nonvolatile Memory

Abstract

This paper presents a novel TaN-Al2O3-HfSiOx-SiO2-silicon (TAHOS) nonvolatile memory (NVM) design with dipole engineering at the HfSiOx/SiO2 interface. The threshold voltage shift achieved by using dipole engineering could enable work function adjustment for NVM devices. The dipole layer at the tunnel oxide–charge storage layer interface increases the programming speed and provides satisfactory retention. This NVM device has a high program/erase (P/E) speed; a 2-V memory window can be achieved by applying 16 V for 10 μs. Regarding high-temperature retention characteristics, 62% of the initial memory window was maintained after 103 P/E-cycle stress in a 10-year simulation. This paper discusses the performance improvement enabled by using dipole layer engineering in the TAHOS NVM.

New n-p Junction Floating Gate to Enhance the Operation Performance of a Semiconductor Memory Device

“…In particular, the tunneling oxide will be more seriously damaged with more programming and erasing sequences, resulting in more charge leakage [ 15 ]. In order to overcome the issue of charge leakage, many device structures have been proposed, e.g., SONOS, BE-SONOS, TAHOS and 3D FLASH [ 6 , 17 , 18 , 19 , 20 ]. The 3D NAND FLASH structure was proposed as a solution when 2D NAND FLASH reached the scaling limit of a 15 nm process node [ 21 ].…”