Chapter 2 Elements of High‐Performance Reconfigurable Computing

VanCourt, T.; Herbordt, Martin C.

doi:10.1016/s0065-2458(08)00802-4

Cited by 3 publications

(3 citation statements)

References 55 publications

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“…(Chiu et al, 2008;Chiu and Herbordt, 2009) (Herbordt, 2013) researched the approaches of the architecture/algorithm codesign of MD processors. (Herbordt et al, 2007;Herbordt et al, 2008;Khan et al, 2013;Vancourt and Herbordt, 2009) provide general overviews of these methods.…”

Section: Previous Work Of 3d Ffts On Fpgasmentioning

confidence: 99%

High Performance Communication on Reconfigurable Clusters

Sheng

Yang

Herbordt

2018

2018 28th International Conference on Field Programmable Logic and Applications (FPL)

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High Performance Computing (HPC) has matured to where it is an essential third pillar, along with theory and experiment, in most domains of science and engineering. Communication latency is a key factor that is limiting the performance of HPC, but can be addressed by integrating communication into accelerators. This integration allows accelerators to communicate with each other without CPU interactions, and even bypassing the network stack. Field Programmable Gate Arrays (FPGAs) are the accelerators that currently best integrate communication with computation. The large number of Multi-gigabit Transceivers (MGTs) on most high-end FPGAs can provide high-bandwidth and low-latency inter-FPGA connections. Additionally, the reconfigurable FPGA fabric enables tight coupling between computation kernel and network interface. Our thesis is that an application-aware communication infrastructure for a multi-FPGA system makes substantial progress in solving the HPC communication bottleneck. This dissertation aims to provide an application-aware solution for communication infrastructure for FPGA-centric clusters. Specifically, our solution demonstrates application-awareness across multiple levels in the network stack, including low-level vii link protocols, router microarchitectures, routing algorithms, and applications. We start by investigating the low-level link protocol and the impact of its latency variance on performance. Our results demonstrate that, although some link jitter is always present, we can still assume near-synchronous communication on an FPGAcluster. This provides the necessary condition for statically-scheduled routing. We then propose two novel router microarchitectures for two different kinds of workloads: a wormhole Virtual Channel (VC)-based router for workloads with dynamic communication, and a statically-scheduled Virtual Output Queueing (VOQ)-based router for workloads with static communication. For the first (VC-based) router, we propose a framework that generates application-aware router configurations. Our results show that, by adding application-awareness into router configuration, the network performance of FPGA clusters can be substantially improved. For the second (VOQbased) router, we propose a novel offline collective routing algorithm. This shows a significant advantage over a state-of-the-art collective routing algorithm. We apply our communication infrastructure to a critical strong-scaling HPC kernel, the 3D FFT. The experimental results demonstrate that the performance of our design is faster than that on CPUs and GPUs by at least one order of magnitude (achieving strong scaling for the target applications). Surprisingly, the FPGA cluster performance is similar to that of an ASIC-cluster. We also implement the 3D FFT on another multi-FPGA platform: the Microsoft Catapult II cloud. Its performance is also comparable or superior to CPU and GPU HPC clusters. The second application we investigate is Molecular Dynamics Simulation (MD). We model MD on both FPGA clouds and clusters. We find ...

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Section: Previous Work Of 3d Ffts On Fpgasmentioning

confidence: 99%

High Performance Communication on Reconfigurable Clusters

Sheng

Yang

Herbordt

2018

2018 28th International Conference on Field Programmable Logic and Applications (FPL)

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“…We briefly state our assumptions about the target HPRC architecture: They are typical for current products; details of appropriate FPGA-based systems can be found, for example, in Hauck and DeHon [2008] and VanCourt and Herbordt [2009].…”

Section: MD System Designmentioning

confidence: 99%

Molecular Dynamics Simulations on High-Performance Reconfigurable Computing Systems

Chiu

Herbordt

2010

ACM Trans. Reconfigurable Technol. Syst.

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The acceleration of molecular dynamics (MD) simulations using high-performance reconfigurable computing (HPRC) has been much studied. Given the intense competition from multicore and GPUs, there is now a question whether MD on HPRC can be competitive. We concentrate here on the MD kernel computation: determining the short-range force between particle pairs. In one part of the study, we systematically explore the design space of the force pipeline with respect to arithmetic algorithm, arithmetic mode, precision, and various other optimizations. We examine simplifications and find that some have little effect on simulation quality. In the other part, we present the first FPGA study of the filtering of particle pairs with nearly zero mutual force, a standard optimization in MD codes. There are several innovations, including a novel partitioning of the particle space, and new methods for filtering and mapping work onto the pipelines. As a consequence, highly efficient filtering can be implemented with only a small fraction of the FPGA’s resources. Overall, we find that, for an Altera Stratix-III EP3ES260, 8 force pipelines running at nearly 200 MHz can fit on the FPGA, and that they can perform at 95% efficiency. This results in an 80-fold per core speed-up for the short-range force, which is likely to make FPGAs highly competitive for MD.

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“…Today's FPGAs are fast and large enough to allow hardware implementation of various algorithms that work faster compared to their software-only counterparts executing on generalpurpose microprocessors [1], [2], [3], [4], [5]. There is a plethora of research efforts regarding the use of FPGA accelerators to speed up critical parts of computationally-intensive programs.…”

Section: Introductionmentioning

confidence: 99%

FPGA accelerator for floating-point matrix multiplication

Jovanovic

Milutinović

2012

IET Comput. Digit. Tech.

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Abstract:This study treats architecture and implementation of a FPGA accelerator for double-precision floating-point matrix multiplication. The architecture is oriented towards minimising resource utilisation and maximising clock frequency. It employs the block matrix multiplication algorithm which returns the result blocks to the host processor as soon as they are computed. This avoids output buffering, and simplifies placement and routing on the chip. The authors show that such architecture is especially well suited for full-duplex communication links between the accelerator and the host processor. The architecture requires the result blocks to be accumulated by the host processor; however, the authors show that typically more than 99% of all arithmetic operations are performed by the accelerator. The implementation focuses on efficient use of embedded FPGA resources, in order to allow for a large number of processing elements (PEs). Each PE uses 8 Virtex-6 DSP blocks. Both adders and multipliers are deeply pipelined and use several FPGA-specific techniques to achieve small area size and high clock frequency. Finally, the authors quantify the performance of accelerator implemented in Xilinx Virtex-6 FPGA, with 252 PEs running at 403 MHz (achieving 203.1 GFLOPS), by comparing it to DGEMM function from MKL, ACML, GotoBLAS and ATLAS libraries executing on Intel Core2Quad and AMD Phenom X4 microprocessors running at 2.8 GHz. The accelerator performs 4.5 times faster than the fastest processor/library pair.

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Chapter 2 Elements of High‐Performance Reconfigurable Computing

Cited by 3 publications

References 55 publications

High Performance Communication on Reconfigurable Clusters

High Performance Communication on Reconfigurable Clusters

Molecular Dynamics Simulations on High-Performance Reconfigurable Computing Systems

FPGA accelerator for floating-point matrix multiplication

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