2010
DOI: 10.1145/1862648.1862653
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Molecular Dynamics Simulations on High-Performance Reconfigurable Computing Systems

Abstract: The acceleration of molecular dynamics (MD) simulations using high-performance reconfigurable computing (HPRC) has been much studied. Given the intense competition from multicore and GPUs, there is now a question whether MD on HPRC can be competitive. We concentrate here on the MD kernel computation: determining the short-range force between particle pairs. In one part of the study, we systematically explore the design space of the force pipeline with respect to arithmetic algorithm, arithmetic mode, precision… Show more

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Cited by 56 publications
(22 citation statements)
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“…We use the force pipeline specified in a previous study [1]. It uses a mix of 32-bit integer (extended for accumulation) and single precision floating point.…”
Section: Resultsmentioning
confidence: 99%
See 2 more Smart Citations
“…We use the force pipeline specified in a previous study [1]. It uses a mix of 32-bit integer (extended for accumulation) and single precision floating point.…”
Section: Resultsmentioning
confidence: 99%
“…Since multipliers are a critical resource, we also show the two "sphere" filters implemented entirely with logic. The cost of a force pipeline (from [1]) is shown for scale.…”
Section: Full Precisionmentioning
confidence: 99%
See 1 more Smart Citation
“…In fact, the design principle of recon¯gurable computing shifts to formulating the connection among various memory blocks and logic blocks as well as to devising the force pipeline that results in the interatomic forces used for motion integration. 159 Therefore, developers of applications in FPGA need to program the hardware connections every time a new algorithm is adopted. Despite the hardware-level approach, the idea behind the work°ow remains the same as those applied in CPU and GPU.…”
Section: Recon¯gurable Computingmentioning
confidence: 99%
“…Therefore, ASICs are out-of-reach for most researchers, although their performances are quite excellent. A cheap way of hardware acceleration is provided by FPGAs (feild-programmablegate-arrays) 13,14,15 . Although the cost is extremely small compared to ASICs, the design time is still very large.…”
Section: Introductionmentioning
confidence: 99%