Efficient particle-pair filtering for acceleration of molecular dynamics simulation

2010 Fourth International Workshop on High-Performance Reconfigurable Computing Technology and Applications (Hprcta)

2010

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Recent work in the FPGA acceleration of molecular dynamics simulation has shown that including on-the-fly neighbor list calculation (particle filtering) in the device has the potential for an 80× per core speed-up over the CPU-based reference code and so to make the approach competitive with other computing technologies. In this paper we report on progress and challenges in advancing this work towards the creation of a production system, especially one capable of running on a large-scale system such as the Novo-G. The current version consists of an FPGAaccelerated NAMD-lite running on a PC with a Gidel PROCStar III. The most important implementation issues include software integration, handling exclusion, and modifying the force pipeline. In the last of these we have added support for Particle-MeshEwald and augmented the Lennard-Jones calculation with a switching function. In experiments, we find that energy stability so far appears to be acceptable, but that longer simulations are needed. Due primarily to the added complexity of the force pipelines, performance is somewhat diminished from the previous study; we find, however, that porting to a newer (existing) device will more than compensate for this loss.

Section: A Initial Performance Profilementioning

confidence: 97%

Section: Introductionmentioning

confidence: 99%

Towards production FPGA-accelerated molecular dynamics: Progress and challenges

Chiu

2010 Fourth International Workshop on High-Performance Reconfigurable Computing Technology and Applications (Hprcta)

2010

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“…2. MD software system = ProtoMol, FPGA = Altera Stratix III [11], [2]. The significance of the Stratix III is that it has improved floating point support.…”

Section: Polynomial Evaluationmentioning

confidence: 99%

Architecture/algorithm codesign of molecular dynamics processors

2013 Asilomar Conference on Signals, Systems and Computers

2013

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Molecular Dynamics is notable in High PerformanceComputing in that it is both sufficiently critical, and not wellenough served by off-the-shelf processors, that it has been continually targeted with domain-specific architectures. These range from the common, i.e., use of accelerators, to FPGA-centric servers describe here, to full-scale ASIC-based systems (e.g., the Anton processor). The strict constraints on achieving strong scaling leads to novel designs, which in turn suggest restructurings of the underlying algorithms. These in turn suggest some changes to the hardware. We discuss the technological issues involved, the implications of various approaches on architecture/algorithm codesign, and how these are likely to affect future high-end processors, both domain-specific and off-the-shelf.

“…In (Gu et al, 2008), the force pipeline was extensively explored. (Chiu et al, 2008;Chiu and Herbordt, 2009) (Herbordt, 2013) researched the approaches of the architecture/algorithm codesign of MD processors. (Herbordt et al, 2007;Herbordt et al, 2008;Khan et al, 2013;Vancourt and Herbordt, 2009) provide general overviews of these methods.…”

Section: Previous Work Of 3d Ffts On Fpgasmentioning

confidence: 99%

High Performance Communication on Reconfigurable Clusters

Sheng

Yang

2018 28th International Conference on Field Programmable Logic and Applications (FPL)

2018

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High Performance Computing (HPC) has matured to where it is an essential third pillar, along with theory and experiment, in most domains of science and engineering. Communication latency is a key factor that is limiting the performance of HPC, but can be addressed by integrating communication into accelerators. This integration allows accelerators to communicate with each other without CPU interactions, and even bypassing the network stack. Field Programmable Gate Arrays (FPGAs) are the accelerators that currently best integrate communication with computation. The large number of Multi-gigabit Transceivers (MGTs) on most high-end FPGAs can provide high-bandwidth and low-latency inter-FPGA connections. Additionally, the reconfigurable FPGA fabric enables tight coupling between computation kernel and network interface. Our thesis is that an application-aware communication infrastructure for a multi-FPGA system makes substantial progress in solving the HPC communication bottleneck. This dissertation aims to provide an application-aware solution for communication infrastructure for FPGA-centric clusters. Specifically, our solution demonstrates application-awareness across multiple levels in the network stack, including low-level vii link protocols, router microarchitectures, routing algorithms, and applications. We start by investigating the low-level link protocol and the impact of its latency variance on performance. Our results demonstrate that, although some link jitter is always present, we can still assume near-synchronous communication on an FPGAcluster. This provides the necessary condition for statically-scheduled routing. We then propose two novel router microarchitectures for two different kinds of workloads: a wormhole Virtual Channel (VC)-based router for workloads with dynamic communication, and a statically-scheduled Virtual Output Queueing (VOQ)-based router for workloads with static communication. For the first (VC-based) router, we propose a framework that generates application-aware router configurations. Our results show that, by adding application-awareness into router configuration, the network performance of FPGA clusters can be substantially improved. For the second (VOQbased) router, we propose a novel offline collective routing algorithm. This shows a significant advantage over a state-of-the-art collective routing algorithm. We apply our communication infrastructure to a critical strong-scaling HPC kernel, the 3D FFT. The experimental results demonstrate that the performance of our design is faster than that on CPUs and GPUs by at least one order of magnitude (achieving strong scaling for the target applications). Surprisingly, the FPGA cluster performance is similar to that of an ASIC-cluster. We also implement the 3D FFT on another multi-FPGA platform: the Microsoft Catapult II cloud. Its performance is also comparable or superior to CPU and GPU HPC clusters. The second application we investigate is Molecular Dynamics Simulation (MD). We model MD on both FPGA clouds and clusters. We find ...