Channel doping concentration and cell program state dependence on random telegraph noise spatial and statistical distribution in 30 nm NAND flash memory

Abstract

The dependence of spatial and statistical distribution of random telegraph noise (RTN) in a 30 nm NAND flash memory on channel doping concentration NA and cell program state Vth is comprehensively investigated using three-dimensional Monte Carlo device simulation considering random dopant fluctuation (RDF). It is found that single trap RTN amplitude Vth is larger at the center of the channel region in the NAND flash memory, which is closer to the jellium (uniform) doping results since NA is relatively low to suppress junction leakage current. In addition, Vth peak at the center of the channel decreases in the higher Vth state due to the current concentration at the shallow trench isolation (STI) edges induced by the high vertical electrical field through the fringing capacitance between the channel and control gate. In such cases, Vth distribution slope  cannot be determined by only considering RDF and single trap.

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

“…Different values were found in NOR arrays, owing once more to differences in cell design and cycling conditions. Such dependences prompted several works and studies on the optimization of the cell process/architecture in order to reduce the extent of the RTN [124,[126][127][128][129][130][131][132][133][134]. In the NAND array, moreover, the RTN amplitude was shown to depend on the cell position and state along the string [135,136] (because of the different transconductances, depending on the source and drain series resistances) and on the state of cells on adjacent BLs [137] (because of the modification in the electron density profile induced by electrostatic interference).…”

Number of traps and trap depth position on statistical distribution of random telegraph noise in scaled NAND flash memory

“…3(a). 16 NA is 310 17 cm -3 while the punch-through stopper (PTS) layer is adopted at 30 nm below the source/drain junction to suppress the excess-short-channel effect. [24][25][26][27][28] The PTS doping concentration is 910 17 cm -3 .…”

“…3(a). 16) The coordinates of the channel length, width, and cell height directions are defined as x, y, and z respectively, as shown in this figure . Figures 3(b) and 3(c) show the cross-section views of the x-z and y-z planes, respectively.…”

“…In our previous work, 16) ΔV th distributions considering a fixed single trap were studied focusing on substrate doping concentration N A in a 30 nm NAND flash memory by threedimensional (3D) Monte Carlo device simulation, as shown in Figs. 2(a) and 2(b).…”