Challenges in TCAD simulations of tunneling field effect transistors

Kampen, C.; Burenkov, A.; Lorenz, J.

doi:10.1109/essderc.2011.6044215

Cited by 11 publications

(3 citation statements)

References 7 publications

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“…For simulating the reverse bias leakage through phonon-assisted tunneling, trap states were introduced at the Schottky interface, with trap energy, concentration, and thickness of the interface as the fitting parameters. Two tunneling paths were defined for electrons to tunnel from the metal to the trap state and for the subsequent tunneling to the conduction band [40]. An electron effective mass value of 0.2 m e was used.…”

Section: Implanted Devicesmentioning

confidence: 99%

Electrical Transport Characteristics of Vertical GaN Schottky-Barrier Diode in Reverse Bias and Its Numerical Simulation

et al. 2023

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We investigated the temperature-dependent reverse characteristics (JR-VR-T) of vertical GaN Schottky-barrier diodes with and without a fluorine-implanted edge termination (ET). To understand the device leakage mechanism, temperature-dependent characterizations were performed, and the observed reverse current was modeled through technology computer-aided design. Different levels of current were observed in both forward and reverse biases for the ET and non-ET devices, which suggested a change in the conduction mechanism for the observed leakages. The measured JR-VR-T characteristics of the non-edge-terminated device were successfully fitted in the entire temperature range with the phonon-assisted tunneling model, whereas for the edge-terminated device, the reverse characteristics were modeled by taking into account the emission of trapped electrons at a high temperature and field caused by Poole–Frenkel emission.

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Section: Implanted Devicesmentioning

confidence: 99%

Electrical Transport Characteristics of Vertical GaN Schottky-Barrier Diode in Reverse Bias and Its Numerical Simulation

et al. 2023

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“…This makes the model in this paper can accurately simulate the changes in electrical and material properties under the high temperature of the strong field. In addition, for the CMOS inverter circuit, a tunneling model of the gate oxide layer is added to the gate oxygen contact surface, which can better reflect the gate leakage current in the experiment [ 22 ].…”

Section: Esd Protection Circuit Modelmentioning

confidence: 99%

Study on ESD Protection Circuit by TCAD Simulation and TLP Experiment

Chai

Liu

et al. 2023

Micromachines

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The anti-ESD characteristic of the electronic system is paid more and more attention. Moreover, the on-chip electrostatic discharge (ESD) is necessary for integrated circuits to prevent ESD failures. In this paper, the mixed TCAD model of the ESD protection circuit is built and simulated, and the negative transmission line pulse (TLP) injection damage experiment is carried out on the CD4069UBC chip. The circuit model consists of three-dimensional shallow trench isolation (STI) diode TCAD models and a three-dimensional multi-gate Complementary Metal-Oxide-Semiconductor (CMOS) inverter TCAD model. Moreover, the TCAD modeling is based on a 0.25 μm technology node. Through the transient simulation of the electrothermal coupling, the electrical signal of the input and output nodes of the circuit and the distribution of the electrothermal parameters in the device are obtained. Moreover, by analyzing the simulation results, the physical phenomena and the mechanisms of interference and damage mechanism during TLP injection are explained. The location and type of diode damage in the TLP injection simulation results of the circuit model are consistent with the TLP experiment damage results. The proposed ESD protection circuit model and analysis method are beneficial to ESD robustness prediction and ESD soft damage analysis of IC.

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“…The body thickness, Ge mole fraction, gate, source, channel, and drain length were kept unchanged to maintain the dimensionality effects captured for all SiGe/Si TFET simulations. Furthermore, Schenk Trap Assisted Tunneling and Shockley‐Read‐Hall recombination models are used to capture defect assisted leakage and the impact of carrier lifetimes 29 . High source doping induced band shrinking effects are captured using the OldSlotBoom bandgap narrowing model 30 .…”

Section: Device Structure and Simulation Setupmentioning

confidence: 99%

Heterodielectric oxide‐engineered single‐lateral pocket‐based gated source TFET

Ashita

Loan

Alkhammash

et al. 2021

Int J Numerical Modelling

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In this work, we propose and investigate a new pocket‐based Si0.55Ge0.45/Si gate normal tunnel FET design employing a gate over source with a single lateral pocket (GSLP) with and without a heterogeneous dielectric (HD) gate oxide. Miller capacitance is significantly reduced with the GSLP design, which is further improved by the HD gate oxide leading to full overshoot/undershoot suppression capability in transient response. Further, a steep switching with more than one order improvement in ON current is achieved when compared to state‐of‐the‐art line pocket designs. As a result, an ~98.8% and ~88% improved intrinsic delay (CGGVDD/ION) is achieved in comparison to dual line pocket and non‐pocketed designs, respectively. Additionally, an improved worst‐case trap‐charge tolerance, reduced pocket‐width‐induced fluctuations, and excellent immunity to gate misalignment‐induced fluctuations are achievable just by replacing the gate‐aligned parallel‐line pockets with a vertically aligned single‐lateral pocket (LP) improving the design reliability. A Ge/Si HD‐GSLP TFET design further offers stable ON currents with SS < 60 mV/dec over a feasible range of pocket widths between ~6 and 8 nm at VDS = VGS = 0.7 V.

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Challenges in TCAD simulations of tunneling field effect transistors

Cited by 11 publications

References 7 publications

Electrical Transport Characteristics of Vertical GaN Schottky-Barrier Diode in Reverse Bias and Its Numerical Simulation

Electrical Transport Characteristics of Vertical GaN Schottky-Barrier Diode in Reverse Bias and Its Numerical Simulation

Study on ESD Protection Circuit by TCAD Simulation and TLP Experiment

Heterodielectric oxide‐engineered single‐lateral pocket‐based gated source TFET

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