Challenges in advanced semiconductor technology in the ulsl era for computer applications

Osburn, C. M.

doi:10.1007/bf02653360

Cited by 19 publications

(16 citation statements)

References 85 publications

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“…[1]. For example, third (100) wafers heat-treated at temperatures T -< 1000~ exhibited similar etch structures to those seen on first wafers, except that the etch pit density was greatly decreased, as was the size of the individual pits.…”

Section: Resultsmentioning

confidence: 81%

“…[1]) increases exponentially with temperature, it is obvious that to understand the isotropic-anisotropic behavior better, times of the thermal treatments should be chosen such that the same amount of silicon is etched away for each temperature employed. An interesting sidelight of the earlier work, once the cause of the etching was determined, was the anisotropy, or the lack of it, of the etching process, as a function of temperature.…”

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confidence: 99%

“…and 4 in. Since the previous study (2) showed that the reaction [1] proceeds to different degree in different regions of the wafers, depending upon the proximity of these regions to the fused silica carrier rails, SEM micrographs were taken at: the center of wafers, the region within the slots of the rails, and the region adjacent to the rails. Before use, all wafers were cleaned by a modified standard technique (10), and then dried by blowing filtered nitrogen across them.…”

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confidence: 99%

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Further Comments on the Thermal Etching of Silicon: The Surface Morphology of (100), (111) and (110) Wafers in the Temperature Range 900°–1150°C

Reisman

Temple

Smith

1990

J. Electrochem. Soc.

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In a previous study it was found that when p-type (100) silicon wafers in a fused quartz wafer carrier were annealed in argon in the temperature range 900~176SiQ migrated over the Si wafer surface and etched it. In this initial study, experiments were isochronal, so that different degrees of etching occurred at each temperature studied. In the present study, the heat-treatments were conducted in a high purity argon atmosphere for periods of time so chosen that at each temperature an approximately equal weight loss of silicon, due to the etching process, could be expected. The effects of heat-treatment on the resulting surface morphology of etch structures of (100), (110), or (111) silicon wafers were compared. It was found under these equal weight loss conditions that the etching at T -< 1000~ is anisotropic (polyhedron etch pits are observed) while at higher temperatures a close to isotropic behavior is observed. It is believed that the crystallographic etch structure generation in the anisotropic etching regime begins at crystal lattice defect sites or at impurity inhomogeneities. In addition to the crystallographic etch pit structures, there is observed at very high magnifications, 9000 times, a slight background structure in the anisotropic etching regime. Here, it is believed that this background structure is the beginning of crystallographically defined etch pits, originating again at some sort of crystal defect. In the isotropic regime, where a similar background structure is also observed, but where crystallographic etch pits are not, it is believed that this again represents crystal defects or impurity inhomogeneities being etched at different rates than the lattice planes, but where lattice plane confinement can no longer take place. It is proposed that the transition from the anisotropic to isotropic surface etching is related to the etching rates for different crystallographic orientations becoming essentially equal at higher temperatures. The technique of high temperature annealing in an inert gas atmosphere appears to represent a sensitive way of revealing defects and impurity distribution in crystalline silicon.) unless CC License in place (see abstract). ecsdl.org/site/terms_use address. Redistribution subject to ECS terms of use (see 142.58.129.109 Downloaded on 2015-06-15 to IP

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Section: Resultsmentioning

confidence: 81%

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confidence: 99%

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confidence: 99%

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Further Comments on the Thermal Etching of Silicon: The Surface Morphology of (100), (111) and (110) Wafers in the Temperature Range 900°–1150°C

Reisman

Temple

Smith

1990

J. Electrochem. Soc.

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“…As a result of the decrease in device dimensions in ultra very large scale integration (UVLSI), ultra shallow p±n junction formation is becoming a challenging task in the submicron complementary metal oxide semiconductor (CMOS) technology [1]. A promising technique to achieve ultra shallow junctions was recently proposed [2 to 6] and it is based on using a silicide as a diffusion source (SADS).…”

Section: Introductionmentioning

confidence: 99%

Refinements on the Diffusion into the Underlying Silicon of Dopants Implanted in a Silicide Layer

Sinder

1998

phys. stat. sol. (a)

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“…As we move from the very large scale integrated (VLSI) circuit arena (216 -221 devices/chip) to the ultra large scale integrated (ULSI) circuit area (2 21 -226 devices/chip) [Osburn and Reisman 1987;Reisman 1983], device dimensions shrink (scale) accordingly. For example, Figure 1 depicts a possible version of a 0.5/~m CMOS device structure in cross section.…”

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confidence: 99%

Ionizing radiation effects on ULSI device yield and reliability

Reisman

1990

J Supercomput

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In terms of initial device yield, and long-term reliability, process-induced radiation damage represents an area of considerable concern. The processes that need to be examined include ion implantation, X-ray, Ebeam and ion beam lithography, electron beam metal evaporation, sputtering, reactive ion etching, and even SEM examination. The paper discusses the effects of synchrotron X-radiation in the energy range 300-1000eV, as well as AI Kc~ exposures which simulate X-ray lithographic procedures. It describes such effects in the context of preliminary studies dealing with varying rad (SiOz) exposure levels at a constant gate insulator thickness, as well as the behavior at several rad exposure levels, as a function of gate insulator thickness. Data are presented showing that despite prevailing beliefs, damage in the synchrotron range follows a linear relationship over the thickness range form less than 10nm to 50nm, indicating strongly that damage resides near the interface and is constant with increasing insulator thickness. It is shown that such behavior is consistent with a simple model. Even if such damage can be annealed completely using normal techniques, which is questionable, there are wide-ranging implications concerning the rad hardness of scaled devices.

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Challenges in advanced semiconductor technology in the ulsl era for computer applications

Cited by 19 publications

References 85 publications

Further Comments on the Thermal Etching of Silicon: The Surface Morphology of (100), (111) and (110) Wafers in the Temperature Range 900°–1150°C

Further Comments on the Thermal Etching of Silicon: The Surface Morphology of (100), (111) and (110) Wafers in the Temperature Range 900°–1150°C

Refinements on the Diffusion into the Underlying Silicon of Dopants Implanted in a Silicide Layer

Ionizing radiation effects on ULSI device yield and reliability

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