Further Comments on the Thermal Etching of Silicon: The Surface Morphology of (100), (111) and (110) Wafers in the Temperature Range 900°–1150°C

Abstract

In a previous study it was found that when p-type (100) silicon wafers in a fused quartz wafer carrier were annealed in argon in the temperature range 900~176SiQ migrated over the Si wafer surface and etched it. In this initial study, experiments were isochronal, so that different degrees of etching occurred at each temperature studied. In the present study, the heat-treatments were conducted in a high purity argon atmosphere for periods of time so chosen that at each temperature an approximately equal weight loss of silicon, due to the etching process, could be expected. The effects of heat-treatment on the resulting surface morphology of etch structures of (100), (110), or (111) silicon wafers were compared. It was found under these equal weight loss conditions that the etching at T -< 1000~ is anisotropic (polyhedron etch pits are observed) while at higher temperatures a close to isotropic behavior is observed. It is believed that the crystallographic etch structure generation in the anisotropic etching regime begins at crystal lattice defect sites or at impurity inhomogeneities. In addition to the crystallographic etch pit structures, there is observed at very high magnifications, 9000 times, a slight background structure in the anisotropic etching regime. Here, it is believed that this background structure is the beginning of crystallographically defined etch pits, originating again at some sort of crystal defect. In the isotropic regime, where a similar background structure is also observed, but where crystallographic etch pits are not, it is believed that this again represents crystal defects or impurity inhomogeneities being etched at different rates than the lattice planes, but where lattice plane confinement can no longer take place. It is proposed that the transition from the anisotropic to isotropic surface etching is related to the etching rates for different crystallographic orientations becoming essentially equal at higher temperatures. The technique of high temperature annealing in an inert gas atmosphere appears to represent a sensitive way of revealing defects and impurity distribution in crystalline silicon.) unless CC License in place (see abstract). ecsdl.org/site/terms_use address. Redistribution subject to ECS terms of use (see 142.58.129.109 Downloaded on 2015-06-15 to IP

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