Challenges and Limitations for Very High Throughput Decoder Architectures for Soft-Decoding

Wehn, Norbert; Scholl, Stefan; Schläfer, Philipp; Lehnigk-Emden, Timo; Alles, Matthias

doi:10.1007/978-3-319-10569-7_2

Cited by 5 publications

(9 citation statements)

References 36 publications

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“…The selected turbo decoder provides the highest gain at the lowest code rate from the selected decoders, but it requires 28 times more resources than the largest RS. Moreover, it is proven in [13], [14] that turbo decoders have internal decoding dependencies and design of high-speed parallel implementation in hardware is difficult.…”

Section: B Selection Of Fec Algorithmmentioning

confidence: 99%

Data Link Layer Processor for 100 Gbps Terahertz Wireless Communications in 28 nm CMOS Technology

et al. 2019

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In this paper, we show our 165 Gbps data link layer processor for wireless communication in the terahertz band. The design utilizes interleaved Reed-Solomon codes with dedicated link adaptation, fragmentation, aggregation, and hybrid-automatic-repeat-request. The main advantage is the low-chip area required to fabricate the processor, which is at least two times lower than the area of low-density paritycheck decoders. Surprisingly, our solution loses only ∼1 dB gain when compared to high-speed low-density parity-check decoders. Moreover, with only 2.38 pJ/bit of energy consumption at 0.8 V, one of the best results in the class of comparable implementations has been achieved. Alongside, we show our vision of a complete 100 Gbps wireless transceiver, including radio frequency frontend and baseband processing. For the baseband realization, we propose a parallel sequence spread spectrum and channel combining at the baseband level. Challenges to high-speed wireless transmission at the terahertz band are addressed as well. To the authors' best knowledge, it is one of the first data link layer implementations that deal with a data rate of ≥ 100 Gbps. INDEX TERMS 100 Gbps wireless, terahertz communication, Reed-Solomon coding, data link layer. The associate editor coordinating the review of this manuscript and approving it for publication was Khursheed Aurangzeb. FIGURE 1. Discussed wireless radio-transceiver system. and baseband implementations. Fig. 1 depicts the architecture of the discussed wireless radio-transceiver. A. CHALLENGES TO HIGH-SPEED WIRELESS COMMUNICATIONS Ultra-high speed wireless systems require either very high bandwidth or very high bandwidth efficiency. In cellular architectures like LTE or 5G high bandwidth efficiency is in the focus. This is due to the limited bandwidth in the available radio bands. Increasing the bandwidth efficiency requires a corresponding increase in signal processing power

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Section: B Selection Of Fec Algorithmmentioning

confidence: 99%

Data Link Layer Processor for 100 Gbps Terahertz Wireless Communications in 28 nm CMOS Technology

et al. 2019

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“…Fig. 1 shows the graph representation of a (16,12) polar code where the blue-dashed-circled v represents a concatenation of two codes of length 4, a (4, 1) polar code with a (4, 3) one, yielding an (8, 4) polar code.…”

Section: A Constructionmentioning

confidence: 99%

“…codes of very high rate offer negligible coding gain over an uncoded communication. For example, among the four constituent codes of length 4 included in the (16,12) polar code illustrated in Fig. 2a, two of them are rate-1 constituent codes.…”

Section: About Constituent Codes: Frozen Bit Locations Rate and Pmentioning

confidence: 99%

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Multi-Mode Unrolled Architectures for Polar Decoders

Giard

Sarkis

Thibeault

et al. 2016

IEEE Trans. Circuits Syst. I

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In this work, we present a family of architectures for polar decoders using a reduced-complexity successivecancellation decoding algorithm that employs unrolling to achieve extremely high throughput values while retaining moderate implementation complexity. The resulting fully-unrolled, deeplypipelined architecture is capable of achieving a coded throughput in excess of 1 Tbps on a 65 nm ASIC at 500 MHz-three orders of magnitude greater than current state-of-the-art polar decoders. However, unrolled decoders are built for a specific, fixed code. Therefore we also present a new method to enable the use of multiple code lengths and rates in a fully-unrolled polar decoder architecture. This method leads to a length-and rate-flexible decoder while retaining the very high speed typical to unrolled decoders. The resulting decoders can decode a master polar code of a given rate and length, and several shorter codes of different rates and lengths. We present results for two versions of a multimode decoder supporting eight and ten different polar codes, respectively. Both are capable of a peak throughput of 25.6 Gbps. For each decoder, the energy efficiency for the longest supported polar code is shown to be of 14.8 pJ/bit at 250 MHz and of 8.8 pJ/bit at 500 MHz.

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“…Notably, in [64], [65], the authors propose a fully-unrolled deeplypipelined decoder for an LDPC code. Polar codes are more suitable to unrolling as they do not feature a complex interleaver like LDPC codes.…”

Section: Architecture Operations and Processing Nodesmentioning

confidence: 99%