Cellular Multiadaptive Analogic Architecture: A Computational Framework for UAV Applications

correspondence between the sensors and the processors, and the sensor and processor arrays are mapped into each other. Since the processors in these implementations occupy significant silicon area, the pitch size of these sensor-processor chips is between 50-200 microns. This yields a low fill-factor (5-15%); moreover, it prevents building high resolution (like 1024x1024) arrays. The largest operational combined sensor-processor array is the ACE16k [8]. It was implemented on 0.35 micron technology, and its size is 128x128. However, this focal-plane sensor-processor array can easily capture and process up to 50,000 FPS real-time, which makes them the fastest image processor devices in the world; it is not usable in many applications, where higher resolution is required. A new version of the ACE16k, currently under development, will step down to 0.18 micron, and reach roughly 20-micron pitch size and QZIF resolution.Some applications, like surface inspection, image enhancement requires the analysis of the entire image continuously, hence the one-to-one correspondence of the sensors and the processors is needed. In the first part of this paper, we are going to introduce the digital implementation of the cellular sensor-computer architecture. In the third chapter, we describe the instruction set and computational performance. Later on, considerations of the technology scaling down and its effect on the implementation are given. Later on, implementation studies are presented and finally we conclude our work. II. SYSTEM ARCHITECTURE OVERVIEWThe system architecture of the cellular sensor computer is introduced here has been developed to integrate the essential tasks in the same entity, namely the sensing, the tightly coupled parallel processing, and a top level communication and algorithmic control. The name of the game in all focal plane array processor implementation is the spatial resolution. The higher the spatial resolution (pixel count) the more precise image sensing and processing operations can be achieved. This certainly means that we have to minimize all the circuits, to be able to shrink the pitch size as much as possible.In the digital domain, the simplest processor techniques are the bit sliced architectures. Though these processors can deal with a single bit in a clock cycle, in a sequence of clock cycles, it can calculate with arbitrary precision numbers. In image processing applications, 4-16 bits precision is typically enough. The advantage of the architecture is that the execution time is proportional with the precision, which makes possible finding trade-offs between precision and execution time.From implementation point of view, the integration of the different functionalities, like sensing, processing, and control, means a solution for different preferences. These preferences can be high speed sensing, less design effort, or high spatial resolution. The different aims directs to different implementation of the same system idea. Our answers for the above three preferences are the integrated sensor-p...

Section: E Foveal Architecturementioning

confidence: 99%

Digital implementation of cellular sensor‐computers

Földesy

Zarándy

Rekeczky

et al. 2006

“…Its functionality, near-sensorprocessing capability, and topographic architecture are inspired by the Cellular Neural Network Universal Machines [2][3][4][5]. In a typical standalone vision system, we can find sensor, AD converters, processor and memory, and the embedding and communication circuits [6,7]. It is obvious that it is difficult to implement efficiently all these components in a single chip.…”

Section: Introductionmentioning

confidence: 99%

Configurable 3D‐integrated focal‐plane cellular sensor–processor array architecture

Földesy

Zarándy

Rekeczky

2008

SUMMARYMixed-signal cellular visual microprocessor architecture with digital processors is described. An Application Specific Integrated Circuit (ASIC) implementation is also demonstrated. The architecture is composed of a regular sensor readout circuit array, prepared for 3D face-to-face-type integration, and one or several cascaded array of mainly identical (single instruction multiple data, SIMD) processing elements. The individual array elements were derived from the same general Hardware Description Language (HDL) description and could be of different sizes, aspect ratio, and computing resources.

Circuits, computers, and beyond Boolean logic

Roska

2007

SUMMARYHistorically, the invention of the stored programmable computer architecture, introduced by John Von Neumann, was also influenced by electrical circuit implementation aspects, as well as tied to fundamental insight of logic reasoning. It can also be considered as a mind-inspired machine. Since then, the implementation of logic gates, control and memories has developed independently of the architecture. In this paper, after summarizing the main properties of the Cellular Wave Computer, we highlight a few basic properties of this new kind of computer and computing. In particular, phenomena related to (i) the one-pass solution of a set of implicit equations due to real-time spatial array feedback, (ii) the true random signal array generation via the insertion of the continuous physical noise signals, (iii) the finite synchrony radius due to the functional delay of wires, as well as to (iv) biology relevance. We also show that the Cellular Wave Computer is performing spatial-temporal inference that goes beyond Boolean logic, a characteristic of living neural circuits.