Cell designs for self-timed FPGAs

Traver, C.; Reese, R.B.; Thornton, Mitchell A.

doi:10.1109/asic.2001.954693

Cited by 25 publications

(12 citation statements)

References 11 publications

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“…Type-3, proposed in [27] and [5], is to some degree a compromise between types (1) and (2). These proposed architectures keep the traditional logic block structure and introduces the concept of an asynchronous wrapper around it.…”

Section: Related Workmentioning

confidence: 99%

Variation Tolerant AFPGA Architecture

Low

Shang

Xia

et al. 2011

2011 17th IEEE International Symposium on Asynchronous Circuits and Systems

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-This paper describes the realization of an interconnect Delay Insensitive (DI) FPGA architecture with distributed asynchronous control. This architecture maintains the basic block structure of traditional FPGAs allowing the potential use of existing FPGA design tools in block design. This asynchronous FPGA architecture is mainly aimed at tolerating the unpredictable delay variations caused by process and environment variations in current and future VLSI technology nodes and also targets power supply variations, including modes such as dynamic voltage scaling and variable Vdd, such as in applications featuring energy harvesting. This is achieved by making the longer inter-block interconnects DI, keeping the computational logic single-rail, and removing global clocks.

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Section: Related Workmentioning

confidence: 99%

Variation Tolerant AFPGA Architecture

Low

Shang

Xia

et al. 2011

2011 17th IEEE International Symposium on Asynchronous Circuits and Systems

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“…There has been some work that has developed hazard-free synthesis methods to map asynchronous logic to both standard FPGAs (e.g. [5], [22]) as well as FPGAs with support for asynchronous logic (e.g. [4]).…”

Section: A Quasi Delay Insensitive Logicmentioning

confidence: 99%

“…There has also been a some work on prototyping asynchronous logic using commercially available synchronous FPGAs (e.g. [5], [22]). …”

Section: Introductionmentioning

confidence: 99%

Reconfigurable Asynchronous Logic

Manohar

2006

IEEE Custom Integrated Circuits Conference 2006

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Abstract-Challenges in mapping asynchronous logic to a flexible substrate include developing a balance between circuitlevel flexibility, mapping complexity, and logic overhead. We have developed a reconfigurable dataflow architecture that addresses these challenges, and have also created the necessary synthesis flow required to map designs to the architecture. The architecture exploits some of the unique features of asynchronous logic, and attains a performance that significantly exceeds previous asynchronous FPGAs.

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“…The signal between gate G4 and G1 in the PL netlist is a feedback net added to ensure safety. Figure 3 shows a Phased Logic gate [9] (PL4gate) that uses a 4-input Lookup Table (LUT4) for the computation element. The Muller C-element is used to detect operand arrival (a,b,c,d) from the LEDR inputs.…”

Section: Introductionmentioning

confidence: 99%