Cascaded Time Difference Amplifier using Differential Logic Delay Cell

Mandai,; Nakura,; Ikeda, Kazuhiro; Asada,

doi:10.1109/socdc.2009.5423907

Cited by 17 publications

(9 citation statements)

References 5 publications

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“…One is based on differential difference amplifiers in a unity gain buffer configuration [15], which improves input range and gain. 4X TAs [16], [17] use delay cells for different features whose gain is controlled by closed loops. A pulse train time amplifier [18], [19] uses repetitive pulses with a gated delay line to support a programmable gain with quantization.…”

Section: Introductionmentioning

confidence: 99%

All-Digital Mismatched Calibrator and Compensator for SR Latch-Based Variable-Gain Time Amplifier

Chao¹,

Lai²,

Hsu³

2020

IEEE Access

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Two major mismatches in SR latch-based time amplifiers (TA) include input skew, which causes gain imbalance, and loading mismatch, which reduces gain accuracy. Accordingly, we propose an all-digital mismatched self-calibrator and compensator for an SR latch-based variable-gain TA. Tunable matching cells and variable capacitors are built into TAs to compensate for input skew (gain imbalance) and loading mismatch (gain inaccuracy). To ensure that the proposed calibration works efficiently and accurately, the TA must provide at least high and low gains where the low gain calibrates the most significant bit (MSB) and the high gain calibrates the least significant bit (LSB). This self-calibrator costs 4375 gates, and the power consumption is 2.8 mA for the TA gain with 2 and 3.2 mA for the TA gain with 16 at a sampling rate of 10 MHz. INDEX TERMS Mismatch calibration, self-calibration, time amplifier.

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Section: Introductionmentioning

confidence: 99%

All-Digital Mismatched Calibrator and Compensator for SR Latch-Based Variable-Gain Time Amplifier

Chao¹,

Lai²,

Hsu³

2020

IEEE Access

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“…TDAs, which are analogous to voltage amplifiers in analogue-to-digital converters for residue amplification, are used to improve time resolution in TDCs. Various implementations of TDAs utilise dissimilarity in two signal paths, including the latch regeneration time constant [3,5], RC time constant [7], switching delay [8] and charge-pump current [9]. Among the different approaches, using different charge-pump currents on to the same size of capacitors can provide large gains of up to 120 [9].…”

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confidence: 99%

Low‐power programmable high‐gain time difference amplifier with regeneration time control

2014

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A gain controllable SR-latch-based time difference amplifier (TDA) with a gain of up to 150 by controlling the regeneration time constant, especially with programmable transconductance (g m), is presented. The presented g m control uses resistor degeneration at the input switches so that the effective g m is reduced, whereas the time difference gain increases. Unavoidable large crowbar current from the slow regeneration is avoided by shifting to the fast regeneration mode after regeneration is completed, which effectively reduces current consumption by 29.3%.

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“…M5 and M6 are the differential pair. M7 is used for current starving, and M8 is connected to the cross coupled pair, the output switches from the short delay to long delay[45] .…”

mentioning

confidence: 99%

“…Figure 3.20 shows a portion of the delay chain based architecture with differential signalling techniques[17,45,46].…”

mentioning

confidence: 99%

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Linearity Improvement in Vernier Delay Chain Based Time Difference Amplifiers

Ramesh¹

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Time difference amplifiers are used in fluorescence experiments where the input time differences are in picoseconds. The key challenge is to provide the linearity of such amplifiers with sufficient gain over the required input range. This amplifier has a gain greater than 2 ps ps , with the input ranging from 10 pS to 1000 pS. The gain error is found to be less than 10% at a temperature of 25 • C , voltage range of 800mV to 1.2 V. The overall power consumption from simulation is 4 mW. This design uses differential signalling based architecture and is an open loop system to realize these specifications. Initially results of the design were verified using simulation techniques and then the physical implementation was done resulting in an integrated circuit that was fabricated and tested. While the open loop approach in this implementation will make it unable to correct the gain with temperature variations, the circuit has features that can integrate well with a feedback system to convert it to a closed loop system.

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Cascaded Time Difference Amplifier using Differential Logic Delay Cell

Cited by 17 publications

References 5 publications

All-Digital Mismatched Calibrator and Compensator for SR Latch-Based Variable-Gain Time Amplifier

All-Digital Mismatched Calibrator and Compensator for SR Latch-Based Variable-Gain Time Amplifier

Low‐power programmable high‐gain time difference amplifier with regeneration time control

Linearity Improvement in Vernier Delay Chain Based Time Difference Amplifiers

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