Cascaded PLL design for a 90nm CMOS high performance microprocessor

Wong, K.L.; Fayneh, E.; Knoll, Ernest; Law, Raymond H.; Lim, Chee How; Parker, Rachael J.; Wang, Feng; Zhao, Cangsang

doi:10.1109/isscc.2003.1234366

Cited by 21 publications

(9 citation statements)

References 3 publications

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“…1 shows widely used replica-biased PLL (RBPLL) topology [3]. To avoid VCO oscillation and lock acquisition failures due to excessive current from charge pump 2 (CP2), RBPLL architecture requires a chopper circuit at the phase frequency detector (PFD) outputs to limit the maximum phase error seen by the charge pumps [4]. Since all the phase difference information from PFD output is not allowed to get transferred to the control nodes VC1 and VC2, the PLL lock time increases.…”

Section: Introductionsupporting

confidence: 55%

Fast lock scheme for phase-locked loops

Bashir

Ivatury

et al. 2009

2009 IEEE Custom Integrated Circuits Conference

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This paper describes a fast lock scheme for phaselocked loops (PLLs). The proposed scheme utilizes mostly digital logic and control to achieve significant reduction in PLL lock acquisition time, which enables dynamic power cycling for various sub-systems on SOC designs. Multiple Self-Bias PLLs having fast lock schemes were designed to operate at VCO frequencies from 1.6GHz to 5GHz, and fabricated using 65nm CMOS process. Silicon measurements indicate up to 75% reduction in worst-case PLL lock times over the device operating conditions.

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Section: Introductionsupporting

confidence: 55%

Fast lock scheme for phase-locked loops

Bashir

Ivatury

et al. 2009

2009 IEEE Custom Integrated Circuits Conference

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“…In test mode, PLL loop is broken and up / down signals are given by FSM. Tested CP has up, down, tristate, and overlap modes [2]. In all modes, predefined currents should flow through CP.…”

Section: Topology and Implementation Of Programmable Iddq Bicsmentioning

confidence: 99%

“…Investigating the CP current is a good indication of its reliability. A new programmable IDDQ BICS and its test flow for a specific CP [2] are proposed in this paper.…”

Section: Introductionmentioning

confidence: 99%

A new built-in IDDQ testing method using programmable BICS

Maltabas

Ekekon

Margala

2010

2010 15th IEEE European Test Symposium

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The paper presents a novel programmable Built In Current Sensor (BICS) topology in IBM 65 nm CMOS technology. Proposed topology has 2.086 GHz bandwidth and 38.9ps detection time. Moreover, a new built-in IDDQ test flow is proposed. Proposed test flow is applied to a charge pump. The results show 100% fault coverage for the defects that affects the output of the charge pump (CP). 97.87% overall fault coverage is achieved for the same test.

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“…A mobile operating system may change state once every one or two ms, of which about 100 µs is budgeted for PLL re-lock and supply voltage slew [1], [2]. This wastes energy and consumes valuable time that could otherwise be spent on useful data processing.…”

Section: Introductionmentioning

confidence: 99%

“…To ensure lock, PLLs on commercial microprocessors budget thousands of reference clock cycles for adequate design margin under the large range of possible initial phase and frequency errors, as well as process, temperature, and supply voltage variations [2].…”

Section: Introductionmentioning

confidence: 99%