In this work, power minimization method for Varicap Threshold Logic (VcTL) implementations is proposed. In this aspect, characteristics of NMOS and PMOS capacitances are investigated. AND OR gates and full adder (FA) are selected to prove the proposed methodology in IBM 65 nm CMOS technology. It was found that the proposed methodology always provides the minimum power with 48% power savings in OR, 46% in FA and 9% in AND realizations compared to not optimized versions. It is shown that 0.8V supply voltage provides best PDP results for AND-OR topologies.
The paper presents a novel programmable Built In Current Sensor (BICS) topology in IBM 65 nm CMOS technology. Proposed topology has 2.086 GHz bandwidth and 38.9ps detection time. Moreover, a new built-in IDDQ test flow is proposed. Proposed test flow is applied to a charge pump. The results show 100% fault coverage for the defects that affects the output of the charge pump (CP). 97.87% overall fault coverage is achieved for the same test.
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