CASCADE: A Standard Supercell Design Methodology With Congestion-Driven Placement for Three-Dimensional Interconnect-Heavy Very Large-Scale Integrated Circuits

Zhou, Lili; Wakayama, Cherry; Shi, C.-J.R.

doi:10.1109/tcad.2006.888266

Cited by 15 publications

(6 citation statements)

References 20 publications

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“…All 3D floorplans are generated by 3D-STAF [6]. The TSV size (pitch) is assumed to be 5um*5um [4]. As for the simulated annealing scheme, we set the initial temperature to be 100, the accepted ratio 0.8, the cooling ratio 0.8 and the fmal temperature 0.1, and specify the inner loop criterion as a given big number.…”

Section: Resultsmentioning

confidence: 99%

“…Cong [3] proposed a thermal-driven multilevel routing method for 3D ICs, in which S-TSV positions in a "planning window" (on one device layer) were determined by a min-cost max-flow method. Zhou [4] also proposed a min-cost max-flow based S-TSV assignment algorithm considering 3D via density and individual tier congestion, but they did not take into account the wire-length and only consider two-terminal 1 This paper was supported by NSFC 61176022.…”

Section: Introductionmentioning

confidence: 99%

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Through-Silicon-Via assignment for 3D ICs

Dong

Chen

et al. 2011

2011 9th IEEE International Conference on ASIC

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Three-dimensional integrated circuits (3D ICs) can alleviate the interconnect problem coming with the decreasing feature size and increasing integration density, and promise a solution to heterogeneous integration. The inter-layer connection, which is generally implemented by the Through-Silicon-Via (TSV), is a key technology for 3D ICs. In this paper, we propose a unified simulated annealing technology to tackle the TSV assignment problem, including the signal TSV assignment of 3D nets and 3D buses. The experiment results show the effective of the method.

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Through-Silicon-Via assignment for 3D ICs

Dong

Chen

et al. 2011

2011 9th IEEE International Conference on ASIC

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“…This is because of the following reasons. According to [1], the pitch for C4 bumps is around 120μm, which is much larger than that of TSV (1.7μm as shown in [22] and this figure keeps shrinking with technology improvements). In other words, one single test pad can consume area equivalent to hundreds of TSVs (see Fig.…”

Section: Test-pin-count Constraintmentioning

confidence: 99%

Layout-driven test-architecture design and optimization for 3D SoCs under pre-bond test-pin-count constraint

Jiangs

Chakrabarty

et al. 2009

Proceedings of the 2009 International Conference on Computer-Aided Design

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“…In recent years, there has been extensive work in developing new physical design tools for 3D IC design [Das et al 2003;Cong et al 2007;Zhou et al 2006]. However, all these tools are mainly linked to the 3D TSV technology, as the main objective is to minimize the number of TSVs while reducing the wirelength of the routed circuit.…”

Section: Introductionmentioning

confidence: 99%

Cell transformations and physical design techniques for 3D monolithic integrated circuits

Bobba

Chakraborty

Thomas

et al. 2013

J. Emerg. Technol. Comput. Syst.

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3D Monolithic Integration (3DMI), also termed as sequential integration, is a potential technology for future gigascale circuits. In 3DMI technology the 3D contacts, connecting different active layers, are in the order of few 100nm. Given the advantage of such small contacts, 3DMI enables fine-grain (gate-level) partitioning of circuits. In this work we present three cell transformation techniques for standard cell-based ICs with 3DMI technology. As a major contribution of this work, we propose a design flow comprising of a cell transformation technique, cell-on-cell stacking, and a physical design technique (CELONCEL PD ) aimed at placing cells transformed with cell-on-cell stacking. We analyze and compare various cell transformation techniques for 3DMI technology without disrupting the regularity of the IC design flow. Our experiments demonstrate the effectiveness of CELONCEL design technique, yielding us an area reduction of 37.5%, 16.2% average reduction in wirelength, and 6.2% average improvement in overall delay, compared with a 2D case when benchmarked across various designs in 45nm technology node.

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CASCADE: A Standard Supercell Design Methodology With Congestion-Driven Placement for Three-Dimensional Interconnect-Heavy Very Large-Scale Integrated Circuits

Cited by 15 publications

References 20 publications

Through-Silicon-Via assignment for 3D ICs

Through-Silicon-Via assignment for 3D ICs

Layout-driven test-architecture design and optimization for 3D SoCs under pre-bond test-pin-count constraint

Cell transformations and physical design techniques for 3D monolithic integrated circuits

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