Carry checking/parity prediction adders and ALUs

Nicolaidis, M.

doi:10.1109/tvlsi.2002.800526

Cited by 105 publications

(52 citation statements)

References 10 publications

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“…Nicolaidis employed parity prediction and double rail checking together to devise a self-checking mechanism for ALUs and adders. Furthermore, different hardware reduction techniques were used to minimize the cost [27].…”

Section: Related Workmentioning

confidence: 99%

Low-Cost Fault Tolerant Methodology for Real Time MPSoC Based Embedded System

Amin

Shakir

Javed

et al. 2014

International Journal of Reconfigurable Computing

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We are proposing a design methodology for a fault tolerant homogeneous MPSoC having additional design objectives that include low hardware overhead and performance. We have implemented three different FT methodologies on MPSoCs and compared them against the defined constraints. The comparison of these FT methodologies is carried out by modelling their architectures in VHDL-RTL, on Spartan 3 FPGA. The results obtained through simulations helped us to identify the most relevant scheme in terms of the given design constraints.

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Section: Related Workmentioning

confidence: 99%

Low-Cost Fault Tolerant Methodology for Real Time MPSoC Based Embedded System

Amin

Shakir

Javed

et al. 2014

International Journal of Reconfigurable Computing

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“…The fault coverage of the presented adder can be tested as described in [23]. Briefly, it can be stated that the faults on the carry signals are detected using the double rail checkers because all errors are propagated through the checker tree.…”

Section: Self Checking Addermentioning

confidence: 99%

Self-checking ripple-carry adder with Ambipolar Silicon NanoWire FET

Turkyilmaz

Clermidy

Amarù

et al. 2013

2013 IEEE International Symposium on Circuits and Systems (ISCAS2013)

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Abstract-For the rapid adoption of new and aggressive technologies such as ambipolar Silicon NanoWire (SiNW), addressing fault-tolerance is necessary. Traditionally, transient fault detection implies large hardware overhead or performance decrease compared to permanent fault detection. In this paper, we focus on on-line testing and its application to ambipolar SiNW. We demonstrate on self-checking ripple-carry adder how ambipolar design style can help reduce the hardware overhead. When compared with equivalent CMOS process, ambipolar SiNW design shows a reduction in area of at least 56% (28%) with a decreased delay of 62% (6%) for Static (Transmission Gate) design style.

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“…We give thereby preliminary research directions towards selfcalibrating adder circuits independent of worst-case assumptions about the adder itself. The discussion expands on prior work about parity prediction for adders and ALUs [9].…”

Section: Extension To Computationmentioning

confidence: 83%

Designing Robust Checkers in the Presence of Massive Timing Errors

Worm

Thiran

Ienne

12th IEEE International on-Line Testing Symposium (IOLTS'06)

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So far, performance and reliability of circuits have been determined by worst-case characterization of silicon and environmental noise. As new deep sub-micron technologies exacerbate process variations and reduce noise margins, worstcase design will eventually fail to meet an aggressive combination of objectives in performance, reliability, and power. In order to circumvent these difficulties, researchers have recently proposed a new design paradigm: self-calibrating circuits. Design parameters (e.g., operating points) of selfcalibrating circuits are set by monitoring correctness of their operation, thus enabling to dynamically trade reliability for power or performance, depending on actual silicon capabilities and noise conditions.In this paper, we study the problem of detecting errors caused by self-calibration of the supply voltage and frequency of an on-chip link. These errors are caused by operation at sub-critical voltage and may be numerous. We attack the problem with a coding technique. We also discuss an alternative approach using double sampling flip-flops. We stress the complementarity of the two approaches and show how they can be combined. Finally, we consider extending our work to computation. We give preliminary research directions on the detection of errors induced by self-calibration for an adder.

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Carry checking/parity prediction adders and ALUs

Cited by 105 publications

References 10 publications

Low-Cost Fault Tolerant Methodology for Real Time MPSoC Based Embedded System

Low-Cost Fault Tolerant Methodology for Real Time MPSoC Based Embedded System

Self-checking ripple-carry adder with Ambipolar Silicon NanoWire FET

Designing Robust Checkers in the Presence of Massive Timing Errors

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